dds_vhdl.map.summary

来自「基于fpga的正弦波发生器设计」· SUMMARY 代码 · 共 11 行

Analysis & Synthesis Status : Successful - Wed Nov 22 19:37:52 2006
Quartus II Version : 6.0 Build 178 04/27/2006 SJ Full Version
Revision Name : dds_vhdl
Top-level Entity Name : dds_vhdl
Family : Cyclone
Total logic elements : 203
Total pins : 41
Total virtual pins : 0
Total memory bits : 10,240
Total PLLs : 1