adder32b.vhd

来自「基于fpga的正弦波发生器设计」· VHDL 代码 · 共 11 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
entity adder32b is
	port(	a,b:	in	std_logic_vector(31 downto 0);
		 	s:	out	std_logic_vector(31 downto 0));
end adder32b;
architecture behav of adder32b is
	begin
	s<=a+b;
end behav;