reg10b.vhd

基于fpga的正弦波发生器设计

library ieee;--10位寄存器模块
use ieee.std_logic_1164.all;
entity reg10b is
	port(load,rst10:	in  std_logic;
		din:	in  std_logic_vector(9 downto 0);
		dout:	out std_logic_vector(9 downto 0));
end reg10b;
architecture behav of reg10b is
begin
	process(load,din,rst10)
	begin
		if rst10='0' then dout<=(others=>'0');
			elsif load'event and load ='1' then dout<=din;
		end if;
	end process;
end behav;