and2.vhd

来自「基于fpga的正弦波发生器设计」· VHDL 代码 · 共 10 行

library ieee;--与门模块
use ieee.std_logic_1164.all;
entity and2ab is
	port(a,b:	in  std_logic;
		 clock0:out  std_logic);
end and2ab;
architecture behav of and2ab is
begin
	clock0<=a and b;
end behav;