dds_vhdl.fit.eqn

基于fpga的正弦波发生器设计

W1L23 = AMPP_FUNCTION(W1_safe_q[3], W1L92);


--W1_safe_q[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[4] at LC_X12_Y9_N4
--operation mode is arithmetic

W1_safe_q[4] = AMPP_FUNCTION(A1L5, W1_safe_q[4], U1L71, !K1_Q[0], U1_ram_rom_incr_addr, W1L13, W1L23);

--W1L01 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|counter_cella4~COUT at LC_X12_Y9_N4
--operation mode is arithmetic

W1L01 = AMPP_FUNCTION(W1_safe_q[4], W1L13, W1L23);


--W1_safe_q[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[5] at LC_X12_Y9_N5
--operation mode is arithmetic

W1_safe_q[5] = AMPP_FUNCTION(A1L5, W1_safe_q[5], U1L81, !K1_Q[0], U1_ram_rom_incr_addr, W1L01);

--W1L53 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[5]~COUT0 at LC_X12_Y9_N5
--operation mode is arithmetic

W1L53 = AMPP_FUNCTION(W1_safe_q[5]);

--W1L63 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[5]~COUT1 at LC_X12_Y9_N5
--operation mode is arithmetic

W1L63 = AMPP_FUNCTION(W1_safe_q[5]);


--W1_safe_q[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[6] at LC_X12_Y9_N6
--operation mode is arithmetic

W1_safe_q[6] = AMPP_FUNCTION(A1L5, W1_safe_q[6], U1L91, !K1_Q[0], U1_ram_rom_incr_addr, W1L01, W1L53, W1L63);

--W1L83 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[6]~COUT0 at LC_X12_Y9_N6
--operation mode is arithmetic

W1L83 = AMPP_FUNCTION(W1_safe_q[6], W1L53);

--W1L93 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[6]~COUT1 at LC_X12_Y9_N6
--operation mode is arithmetic

W1L93 = AMPP_FUNCTION(W1_safe_q[6], W1L63);


--W1_safe_q[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[7] at LC_X12_Y9_N7
--operation mode is arithmetic

W1_safe_q[7] = AMPP_FUNCTION(A1L5, W1_safe_q[7], U1L02, !K1_Q[0], U1_ram_rom_incr_addr, W1L01, W1L83, W1L93);

--W1L14 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[7]~COUT0 at LC_X12_Y9_N7
--operation mode is arithmetic

W1L14 = AMPP_FUNCTION(W1_safe_q[7], W1L83);

--W1L24 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[7]~COUT1 at LC_X12_Y9_N7
--operation mode is arithmetic

W1L24 = AMPP_FUNCTION(W1_safe_q[7], W1L93);


--W1_safe_q[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[8] at LC_X12_Y9_N8
--operation mode is arithmetic

W1_safe_q[8] = AMPP_FUNCTION(A1L5, W1_safe_q[8], U1L12, !K1_Q[0], U1_ram_rom_incr_addr, W1L01, W1L14, W1L24);

--W1L44 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[8]~COUT0 at LC_X12_Y9_N8
--operation mode is arithmetic

W1L44 = AMPP_FUNCTION(W1_safe_q[8], W1L14);

--W1L54 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[8]~COUT1 at LC_X12_Y9_N8
--operation mode is arithmetic

W1L54 = AMPP_FUNCTION(W1_safe_q[8], W1L24);


--W1_safe_q[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_addr_reg_rtl_0|cntr_8b8:auto_generated|safe_q[9] at LC_X12_Y9_N9
--operation mode is normal

W1_safe_q[9] = AMPP_FUNCTION(A1L5, W1_safe_q[9], U1L22, !K1_Q[0], U1_ram_rom_incr_addr, W1L01, W1L44, W1L54);


--U1_ram_rom_data_reg[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[8] at LC_X15_Y8_N6
--operation mode is normal

U1_ram_rom_data_reg[8] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[9], U1L01, T1_q_b[8], U1_ram_rom_data_reg[8], VCC, U1L9);


--U1_ram_rom_data_reg[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[7] at LC_X15_Y8_N1
--operation mode is normal

U1_ram_rom_data_reg[7] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[7], U1L01, T1_q_b[7], U1_ram_rom_data_reg[8], VCC, U1L9);


--U1_ram_rom_data_reg[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6] at LC_X15_Y8_N2
--operation mode is normal

U1_ram_rom_data_reg[6] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[6], U1L01, T1_q_b[6], U1_ram_rom_data_reg[7], VCC, U1L9);


--U1_ram_rom_data_reg[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[5] at LC_X15_Y8_N8
--operation mode is normal

U1_ram_rom_data_reg[5] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[6], U1L01, T1_q_b[5], U1_ram_rom_data_reg[5], VCC, U1L9);


--U1_ram_rom_data_reg[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[4] at LC_X15_Y8_N3
--operation mode is normal

U1_ram_rom_data_reg[4] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[5], U1L01, T1_q_b[4], U1_ram_rom_data_reg[4], VCC, U1L9);


--U1_ram_rom_data_reg[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[3] at LC_X15_Y8_N7
--operation mode is normal

U1_ram_rom_data_reg[3] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[3], U1L01, T1_q_b[3], U1_ram_rom_data_reg[4], VCC, U1L9);


--U1_ram_rom_data_reg[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[2] at LC_X15_Y8_N5
--operation mode is normal

U1_ram_rom_data_reg[2] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[3], U1L01, T1_q_b[2], U1_ram_rom_data_reg[2], VCC, U1L9);


--U1_ram_rom_data_reg[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[1] at LC_X15_Y8_N0
--operation mode is normal

U1_ram_rom_data_reg[1] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[2], U1L01, T1_q_b[1], U1_ram_rom_data_reg[1], VCC, U1L9);


--U1_ram_rom_data_reg[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[0] at LC_X15_Y8_N9
--operation mode is normal

U1_ram_rom_data_reg[0] = AMPP_FUNCTION(A1L5, U1_ram_rom_data_reg[0], U1L01, T1_q_b[0], U1_ram_rom_data_reg[1], VCC, U1L9);


--B1L51Q is sld_hub:sld_hub_inst|HUB_TDO~reg0 at LC_X12_Y7_N3
--operation mode is normal

B1L51Q = AMPP_FUNCTION(!A1L5, B1L31, B1_jtag_debug_mode_usr1, B1L11, K6_Q[0], !P1_state[8], B1L92);


--X1_safe_q[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1] at LC_X15_Y7_N2
--operation mode is arithmetic

X1_safe_q[1] = AMPP_FUNCTION(A1L5, X1_safe_q[1], U1L01, !K1_Q[3], U1L83, X1L01, X1L11);

--X1L31 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1]~COUT0 at LC_X15_Y7_N2
--operation mode is arithmetic

X1L31 = AMPP_FUNCTION(X1_safe_q[1], X1L01);

--X1L41 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[1]~COUT1 at LC_X15_Y7_N2
--operation mode is arithmetic

X1L41 = AMPP_FUNCTION(X1_safe_q[1], X1L11);


--X1_safe_q[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[2] at LC_X15_Y7_N3
--operation mode is arithmetic

X1_safe_q[2] = AMPP_FUNCTION(A1L5, U1L01, X1_safe_q[2], !K1_Q[3], U1L83, X1L31, X1L41);

--X1L61 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[2]~COUT0 at LC_X15_Y7_N3
--operation mode is arithmetic

X1L61 = AMPP_FUNCTION(X1_safe_q[2], X1L31);

--X1L71 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[2]~COUT1 at LC_X15_Y7_N3
--operation mode is arithmetic

X1L71 = AMPP_FUNCTION(X1_safe_q[2], X1L41);


--X1_safe_q[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[0] at LC_X15_Y7_N1
--operation mode is arithmetic

X1_safe_q[0] = AMPP_FUNCTION(A1L5, X1_safe_q[0], U1L01, !K1_Q[3], U1L83);

--X1L01 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[0]~COUT0 at LC_X15_Y7_N1
--operation mode is arithmetic

X1L01 = AMPP_FUNCTION(X1_safe_q[0]);

--X1L11 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[0]~COUT1 at LC_X15_Y7_N1
--operation mode is arithmetic

X1L11 = AMPP_FUNCTION(X1_safe_q[0]);


--X1_safe_q[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|lpm_counter:ram_rom_data_shift_cntr_reg_rtl_1|cntr_pd8:auto_generated|safe_q[3] at LC_X15_Y7_N4
--operation mode is normal

X1_safe_q[3] = AMPP_FUNCTION(A1L5, U1L01, X1_safe_q[3], !K1_Q[3], U1L83, X1L61, X1L71);


--U1L83 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_load_read_data~17 at LC_X15_Y7_N8
--operation mode is normal

U1L83 = AMPP_FUNCTION(X1_safe_q[0], X1_safe_q[3], X1_safe_q[1], X1_safe_q[2]);

--U1_ram_rom_incr_write_addr_reg is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_write_addr_reg at LC_X15_Y7_N8
--operation mode is normal

U1_ram_rom_incr_write_addr_reg = AMPP_FUNCTION(A1L5, X1_safe_q[0], X1_safe_q[3], X1_safe_q[1], X1_safe_q[2], VCC);


--K2_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|Q[2] at LC_X11_Y7_N7
--operation mode is normal

K2_Q[2] = AMPP_FUNCTION(A1L5, K6_Q[2], !B1L2, B1L8);


--K6_Q[2] is sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[2] at LC_X11_Y8_N1
--operation mode is normal

K6_Q[2] = AMPP_FUNCTION(A1L5, K6_Q[2], U1_ir_loaded_address_reg[1], K6_Q[3], B1L61, !B1L2, P1_state[4], B1_IRSR_ENA);


--P1_state[1] is sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine|state[1] at LC_X9_Y10_N1