📄 dds_vhdl.fit.eqn
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T1_q_a[8]_PORT_A_data_out = MEMORY(T1_q_a[8]_PORT_A_data_in_reg, T1_q_a[8]_PORT_B_data_in_reg, T1_q_a[8]_PORT_A_address_reg, T1_q_a[8]_PORT_B_address_reg, T1_q_a[8]_PORT_A_write_enable_reg, T1_q_a[8]_PORT_B_write_enable_reg, , , T1_q_a[8]_clock_0, T1_q_a[8]_clock_1, , , , );
T1_q_a[8]_PORT_A_data_out_reg = DFFE(T1_q_a[8]_PORT_A_data_out, T1_q_a[8]_clock_0, , , );
T1_q_a[1] = T1_q_a[8]_PORT_A_data_out_reg[3];
--T1_q_a[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[5] at M4K_X13_Y9
T1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_a[8]_PORT_A_data_in_reg = DFFE(T1_q_a[8]_PORT_A_data_in, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[1]);
T1_q_a[8]_PORT_B_data_in_reg = DFFE(T1_q_a[8]_PORT_B_data_in, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[8]_PORT_A_address_reg = DFFE(T1_q_a[8]_PORT_A_address, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[8]_PORT_B_address_reg = DFFE(T1_q_a[8]_PORT_B_address, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_write_enable = GND;
T1_q_a[8]_PORT_A_write_enable_reg = DFFE(T1_q_a[8]_PORT_A_write_enable, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_write_enable = U1L53;
T1_q_a[8]_PORT_B_write_enable_reg = DFFE(T1_q_a[8]_PORT_B_write_enable, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[8]_clock_1 = GLOBAL(A1L5);
T1_q_a[8]_PORT_A_data_out = MEMORY(T1_q_a[8]_PORT_A_data_in_reg, T1_q_a[8]_PORT_B_data_in_reg, T1_q_a[8]_PORT_A_address_reg, T1_q_a[8]_PORT_B_address_reg, T1_q_a[8]_PORT_A_write_enable_reg, T1_q_a[8]_PORT_B_write_enable_reg, , , T1_q_a[8]_clock_0, T1_q_a[8]_clock_1, , , , );
T1_q_a[8]_PORT_A_data_out_reg = DFFE(T1_q_a[8]_PORT_A_data_out, T1_q_a[8]_clock_0, , , );
T1_q_a[5] = T1_q_a[8]_PORT_A_data_out_reg[2];
--T1_q_a[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[7] at M4K_X13_Y9
T1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_a[8]_PORT_A_data_in_reg = DFFE(T1_q_a[8]_PORT_A_data_in, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[1]);
T1_q_a[8]_PORT_B_data_in_reg = DFFE(T1_q_a[8]_PORT_B_data_in, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[8]_PORT_A_address_reg = DFFE(T1_q_a[8]_PORT_A_address, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[8]_PORT_B_address_reg = DFFE(T1_q_a[8]_PORT_B_address, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_write_enable = GND;
T1_q_a[8]_PORT_A_write_enable_reg = DFFE(T1_q_a[8]_PORT_A_write_enable, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_write_enable = U1L53;
T1_q_a[8]_PORT_B_write_enable_reg = DFFE(T1_q_a[8]_PORT_B_write_enable, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[8]_clock_1 = GLOBAL(A1L5);
T1_q_a[8]_PORT_A_data_out = MEMORY(T1_q_a[8]_PORT_A_data_in_reg, T1_q_a[8]_PORT_B_data_in_reg, T1_q_a[8]_PORT_A_address_reg, T1_q_a[8]_PORT_B_address_reg, T1_q_a[8]_PORT_A_write_enable_reg, T1_q_a[8]_PORT_B_write_enable_reg, , , T1_q_a[8]_clock_0, T1_q_a[8]_clock_1, , , , );
T1_q_a[8]_PORT_A_data_out_reg = DFFE(T1_q_a[8]_PORT_A_data_out, T1_q_a[8]_clock_0, , , );
T1_q_a[7] = T1_q_a[8]_PORT_A_data_out_reg[1];
--T1_q_b[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[1] at M4K_X13_Y9
T1_q_b[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_b[8]_PORT_A_data_in_reg = DFFE(T1_q_b[8]_PORT_A_data_in, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[1]);
T1_q_b[8]_PORT_B_data_in_reg = DFFE(T1_q_b[8]_PORT_B_data_in, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[8]_PORT_A_address_reg = DFFE(T1_q_b[8]_PORT_A_address, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[8]_PORT_B_address_reg = DFFE(T1_q_b[8]_PORT_B_address, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_write_enable = GND;
T1_q_b[8]_PORT_A_write_enable_reg = DFFE(T1_q_b[8]_PORT_A_write_enable, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_write_enable = U1L53;
T1_q_b[8]_PORT_B_write_enable_reg = DFFE(T1_q_b[8]_PORT_B_write_enable, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[8]_clock_1 = GLOBAL(A1L5);
T1_q_b[8]_PORT_B_data_out = MEMORY(T1_q_b[8]_PORT_A_data_in_reg, T1_q_b[8]_PORT_B_data_in_reg, T1_q_b[8]_PORT_A_address_reg, T1_q_b[8]_PORT_B_address_reg, T1_q_b[8]_PORT_A_write_enable_reg, T1_q_b[8]_PORT_B_write_enable_reg, , , T1_q_b[8]_clock_0, T1_q_b[8]_clock_1, , , , );
T1_q_b[1] = T1_q_b[8]_PORT_B_data_out[3];
--T1_q_b[5] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[5] at M4K_X13_Y9
T1_q_b[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_b[8]_PORT_A_data_in_reg = DFFE(T1_q_b[8]_PORT_A_data_in, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[1]);
T1_q_b[8]_PORT_B_data_in_reg = DFFE(T1_q_b[8]_PORT_B_data_in, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[8]_PORT_A_address_reg = DFFE(T1_q_b[8]_PORT_A_address, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[8]_PORT_B_address_reg = DFFE(T1_q_b[8]_PORT_B_address, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_write_enable = GND;
T1_q_b[8]_PORT_A_write_enable_reg = DFFE(T1_q_b[8]_PORT_A_write_enable, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_write_enable = U1L53;
T1_q_b[8]_PORT_B_write_enable_reg = DFFE(T1_q_b[8]_PORT_B_write_enable, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[8]_clock_1 = GLOBAL(A1L5);
T1_q_b[8]_PORT_B_data_out = MEMORY(T1_q_b[8]_PORT_A_data_in_reg, T1_q_b[8]_PORT_B_data_in_reg, T1_q_b[8]_PORT_A_address_reg, T1_q_b[8]_PORT_B_address_reg, T1_q_b[8]_PORT_A_write_enable_reg, T1_q_b[8]_PORT_B_write_enable_reg, , , T1_q_b[8]_clock_0, T1_q_b[8]_clock_1, , , , );
T1_q_b[5] = T1_q_b[8]_PORT_B_data_out[2];
--T1_q_b[7] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[7] at M4K_X13_Y9
T1_q_b[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_b[8]_PORT_A_data_in_reg = DFFE(T1_q_b[8]_PORT_A_data_in, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[1]);
T1_q_b[8]_PORT_B_data_in_reg = DFFE(T1_q_b[8]_PORT_B_data_in, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[8]_PORT_A_address_reg = DFFE(T1_q_b[8]_PORT_A_address, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[8]_PORT_B_address_reg = DFFE(T1_q_b[8]_PORT_B_address, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_write_enable = GND;
T1_q_b[8]_PORT_A_write_enable_reg = DFFE(T1_q_b[8]_PORT_A_write_enable, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_write_enable = U1L53;
T1_q_b[8]_PORT_B_write_enable_reg = DFFE(T1_q_b[8]_PORT_B_write_enable, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[8]_clock_1 = GLOBAL(A1L5);
T1_q_b[8]_PORT_B_data_out = MEMORY(T1_q_b[8]_PORT_A_data_in_reg, T1_q_b[8]_PORT_B_data_in_reg, T1_q_b[8]_PORT_A_address_reg, T1_q_b[8]_PORT_B_address_reg, T1_q_b[8]_PORT_A_write_enable_reg, T1_q_b[8]_PORT_B_write_enable_reg, , , T1_q_b[8]_clock_0, T1_q_b[8]_clock_1, , , , );
T1_q_b[7] = T1_q_b[8]_PORT_B_data_out[1];
--T1_q_a[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[6] at M4K_X13_Y7
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 2, Port B Depth: 1024, Port B Width: 2
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[6]_PORT_A_data_in = BUS(VCC, VCC);
T1_q_a[6]_PORT_A_data_in_reg = DFFE(T1_q_a[6]_PORT_A_data_in, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[6], U1_ram_rom_data_reg[3]);
T1_q_a[6]_PORT_B_data_in_reg = DFFE(T1_q_a[6]_PORT_B_data_in, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[6]_PORT_A_address_reg = DFFE(T1_q_a[6]_PORT_A_address, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[6]_PORT_B_address_reg = DFFE(T1_q_a[6]_PORT_B_address, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_PORT_A_write_enable = GND;
T1_q_a[6]_PORT_A_write_enable_reg = DFFE(T1_q_a[6]_PORT_A_write_enable, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_write_enable = U1L53;
T1_q_a[6]_PORT_B_write_enable_reg = DFFE(T1_q_a[6]_PORT_B_write_enable, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[6]_clock_1 = GLOBAL(A1L5);
T1_q_a[6]_PORT_A_data_out = MEMORY(T1_q_a[6]_PORT_A_data_in_reg, T1_q_a[6]_PORT_B_data_in_reg, T1_q_a[6]_PORT_A_address_reg, T1_q_a[6]_PORT_B_address_reg, T1_q_a[6]_PORT_A_write_enable_reg, T1_q_a[6]_PORT_B_write_enable_reg, , , T1_q_a[6]_clock_0, T1_q_a[6]_clock_1, , , , );
T1_q_a[6]_PORT_A_data_out_reg = DFFE(T1_q_a[6]_PORT_A_data_out, T1_q_a[6]_clock_0, , , );
T1_q_a[6] = T1_q_a[6]_PORT_A_data_out_reg[0];
--T1_q_b[6] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[6] at M4K_X13_Y7
T1_q_b[6]_PORT_A_data_in = BUS(VCC, VCC);
T1_q_b[6]_PORT_A_data_in_reg = DFFE(T1_q_b[6]_PORT_A_data_in, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[6], U1_ram_rom_data_reg[3]);
T1_q_b[6]_PORT_B_data_in_reg = DFFE(T1_q_b[6]_PORT_B_data_in, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[6]_PORT_A_address_reg = DFFE(T1_q_b[6]_PORT_A_address, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[6]_PORT_B_address_reg = DFFE(T1_q_b[6]_PORT_B_address, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_PORT_A_write_enable = GND;
T1_q_b[6]_PORT_A_write_enable_reg = DFFE(T1_q_b[6]_PORT_A_write_enable, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_write_enable = U1L53;
T1_q_b[6]_PORT_B_write_enable_reg = DFFE(T1_q_b[6]_PORT_B_write_enable, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[6]_clock_1 = GLOBAL(A1L5);
T1_q_b[6]_PORT_B_data_out = MEMORY(T1_q_b[6]_PORT_A_data_in_reg, T1_q_b[6]_PORT_B_data_in_reg, T1_q_b[6]_PORT_A_address_reg, T1_q_b[6]_PORT_B_address_reg, T1_q_b[6]_PORT_A_write_enable_reg, T1_q_b[6]_PORT_B_write_enable_reg, , , T1_q_b[6]_clock_0, T1_q_b[6]_clock_1, , , , );
T1_q_b[6] = T1_q_b[6]_PORT_B_data_out[0];
--T1_q_a[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[3] at M4K_X13_Y7
T1_q_a[6]_PORT_A_data_in = BUS(VCC, VCC);
T1_q_a[6]_PORT_A_data_in_reg = DFFE(T1_q_a[6]_PORT_A_data_in, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[6], U1_ram_rom_data_reg[3]);
T1_q_a[6]_PORT_B_data_in_reg = DFFE(T1_q_a[6]_PORT_B_data_in, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[6]_PORT_A_address_reg = DFFE(T1_q_a[6]_PORT_A_address, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[6]_PORT_B_address_reg = DFFE(T1_q_a[6]_PORT_B_address, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_PORT_A_write_enable = GND;
T1_q_a[6]_PORT_A_write_enable_reg = DFFE(T1_q_a[6]_PORT_A_write_enable, T1_q_a[6]_clock_0, , , );
T1_q_a[6]_PORT_B_write_enable = U1L53;
T1_q_a[6]_PORT_B_write_enable_reg = DFFE(T1_q_a[6]_PORT_B_write_enable, T1_q_a[6]_clock_1, , , );
T1_q_a[6]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[6]_clock_1 = GLOBAL(A1L5);
T1_q_a[6]_PORT_A_data_out = MEMORY(T1_q_a[6]_PORT_A_data_in_reg, T1_q_a[6]_PORT_B_data_in_reg, T1_q_a[6]_PORT_A_address_reg, T1_q_a[6]_PORT_B_address_reg, T1_q_a[6]_PORT_A_write_enable_reg, T1_q_a[6]_PORT_B_write_enable_reg, , , T1_q_a[6]_clock_0, T1_q_a[6]_clock_1, , , , );
T1_q_a[6]_PORT_A_data_out_reg = DFFE(T1_q_a[6]_PORT_A_data_out, T1_q_a[6]_clock_0, , , );
T1_q_a[3] = T1_q_a[6]_PORT_A_data_out_reg[1];
--T1_q_b[3] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[3] at M4K_X13_Y7
T1_q_b[6]_PORT_A_data_in = BUS(VCC, VCC);
T1_q_b[6]_PORT_A_data_in_reg = DFFE(T1_q_b[6]_PORT_A_data_in, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[6], U1_ram_rom_data_reg[3]);
T1_q_b[6]_PORT_B_data_in_reg = DFFE(T1_q_b[6]_PORT_B_data_in, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[6]_PORT_A_address_reg = DFFE(T1_q_b[6]_PORT_A_address, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[6]_PORT_B_address_reg = DFFE(T1_q_b[6]_PORT_B_address, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_PORT_A_write_enable = GND;
T1_q_b[6]_PORT_A_write_enable_reg = DFFE(T1_q_b[6]_PORT_A_write_enable, T1_q_b[6]_clock_0, , , );
T1_q_b[6]_PORT_B_write_enable = U1L53;
T1_q_b[6]_PORT_B_write_enable_reg = DFFE(T1_q_b[6]_PORT_B_write_enable, T1_q_b[6]_clock_1, , , );
T1_q_b[6]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[6]_clock_1 = GLOBAL(A1L5);
T1_q_b[6]_PORT_B_data_out = MEMORY(T1_q_b[6]_PORT_A_data_in_reg, T1_q_b[6]_PORT_B_data_in_reg, T1_q_b[6]_PORT_A_address_reg, T1_q_b[6]_PORT_B_address_reg, T1_q_b[6]_PORT_A_write_enable_reg, T1_q_b[6]_PORT_B_write_enable_reg, , , T1_q_b[6]_clock_0, T1_q_b[6]_clock_1, , , , );
T1_q_b[3] = T1_q_b[6]_PORT_B_data_out[1];
--A1L6 is altera_internal_jtag~TDO at JTAG_X1_Y6_N1
A1L6 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L51Q);
--A1L7 is altera_internal_jtag~TMSUTAP at JTAG_X1_Y6_N1
A1L7 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L51Q);
--A1L5 is altera_internal_jtag~TCKUTAP at JTAG_X1_Y6_N1
A1L5 = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L51Q);
--altera_internal_jtag is altera_internal_jtag at JTAG_X1_Y6_N1
altera_internal_jtag = STRATIX_ELA(altera_reserved_tms, altera_reserved_tck, altera_reserved_tdi, , , !B1L51Q);
--K1_Q[2] is sld_hub:sld_hub_inst|sld_dffex:\GEN_IRF:1:IRF|Q[2] at LC_X11_Y7_N8
--operation mode is normal
K1_Q[2] = AMPP_FUNCTION(A1L5, K3_Q[0], K2_Q[2], K6_Q[2], !B1L2, B1L91);
--U1L53 is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_incr_addr~1 at LC_X15_Y7_N5
--operation mode is normal
U1L53 = AMPP_FUNCTION(K1_Q[2], U1_ram_rom_incr_write_addr_reg);
--G1_dout[0] is reg10b:u5|dout[0] at LC_X9_Y5_N0
--operation mode is arithmetic
G1_dout[0]_lut_out = D1_dout[22] $ pword[0];
G1_dout[0] = DFFEA(G1_dout[0]_lut_out, GLOBAL(J1_clock0), Y1__locked, , , , );
--G1L4 is reg10b:u5|dout[0]~COUT0 at LC_X9_Y5_N0
--operation mode is arithmetic
G1L4_cout_0 = D1_dout[22] & pword[0];
G1L4 = CARRY(G1L4_cout_0);
--G1L5 is reg10b:u5|dout[0]~COUT1 at LC_X9_Y5_N0
--operation mode is arithmetic
G1L5_cout_1 = D1_dout[22] & pword[0];
G1L5 = CARRY(G1L5_cout_1);
--G1_dout[1] is reg10b:u5|dout[1] at LC_X9_Y5_N1
--operation mode is arithmetic
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