dds_vhdl.fit.eqn

基于fpga的正弦波发生器设计

--Y1__locked is pll1:u6|altpll:altpll_component|_locked at PLL_1
Y1__locked = PLL.LOCKED(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());

--Y1__clk0 is pll1:u6|altpll:altpll_component|_clk0 at PLL_1
Y1__clk0 = PLL.CLK0(.FBIN(), .ENA(), .CLKSWITCH(), .ARESET(), .PFDENA(), .SCANCLK(), .SCANACLR(), .SCANDATA(), .COMPARATOR(), .INCLK(clk), .INCLK(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .CLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA(), .EXTCLKENA());


--J1_clock0 is and2ab:u7|clock0 at LC_X8_Y6_N0
--operation mode is normal

J1_clock0 = Y1__locked & GLOBAL(Y1__clk0);


--T1_q_a[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[9] at M4K_X13_Y8
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_a[9]_PORT_A_data_in_reg = DFFE(T1_q_a[9]_PORT_A_data_in, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[9], U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[0]);
T1_q_a[9]_PORT_B_data_in_reg = DFFE(T1_q_a[9]_PORT_B_data_in, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[9]_PORT_A_address_reg = DFFE(T1_q_a[9]_PORT_A_address, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[9]_PORT_B_address_reg = DFFE(T1_q_a[9]_PORT_B_address, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_write_enable = GND;
T1_q_a[9]_PORT_A_write_enable_reg = DFFE(T1_q_a[9]_PORT_A_write_enable, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_write_enable = U1L53;
T1_q_a[9]_PORT_B_write_enable_reg = DFFE(T1_q_a[9]_PORT_B_write_enable, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[9]_clock_1 = GLOBAL(A1L5);
T1_q_a[9]_PORT_A_data_out = MEMORY(T1_q_a[9]_PORT_A_data_in_reg, T1_q_a[9]_PORT_B_data_in_reg, T1_q_a[9]_PORT_A_address_reg, T1_q_a[9]_PORT_B_address_reg, T1_q_a[9]_PORT_A_write_enable_reg, T1_q_a[9]_PORT_B_write_enable_reg, , , T1_q_a[9]_clock_0, T1_q_a[9]_clock_1, , , , );
T1_q_a[9]_PORT_A_data_out_reg = DFFE(T1_q_a[9]_PORT_A_data_out, T1_q_a[9]_clock_0, , , );
T1_q_a[9] = T1_q_a[9]_PORT_A_data_out_reg[0];

--T1_q_b[9] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[9] at M4K_X13_Y8
T1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_b[9]_PORT_A_data_in_reg = DFFE(T1_q_b[9]_PORT_A_data_in, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[9], U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[0]);
T1_q_b[9]_PORT_B_data_in_reg = DFFE(T1_q_b[9]_PORT_B_data_in, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[9]_PORT_A_address_reg = DFFE(T1_q_b[9]_PORT_A_address, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[9]_PORT_B_address_reg = DFFE(T1_q_b[9]_PORT_B_address, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_write_enable = GND;
T1_q_b[9]_PORT_A_write_enable_reg = DFFE(T1_q_b[9]_PORT_A_write_enable, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_write_enable = U1L53;
T1_q_b[9]_PORT_B_write_enable_reg = DFFE(T1_q_b[9]_PORT_B_write_enable, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[9]_clock_1 = GLOBAL(A1L5);
T1_q_b[9]_PORT_B_data_out = MEMORY(T1_q_b[9]_PORT_A_data_in_reg, T1_q_b[9]_PORT_B_data_in_reg, T1_q_b[9]_PORT_A_address_reg, T1_q_b[9]_PORT_B_address_reg, T1_q_b[9]_PORT_A_write_enable_reg, T1_q_b[9]_PORT_B_write_enable_reg, , , T1_q_b[9]_clock_0, T1_q_b[9]_clock_1, , , , );
T1_q_b[9] = T1_q_b[9]_PORT_B_data_out[0];

--T1_q_a[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[0] at M4K_X13_Y8
T1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_a[9]_PORT_A_data_in_reg = DFFE(T1_q_a[9]_PORT_A_data_in, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[9], U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[0]);
T1_q_a[9]_PORT_B_data_in_reg = DFFE(T1_q_a[9]_PORT_B_data_in, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[9]_PORT_A_address_reg = DFFE(T1_q_a[9]_PORT_A_address, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[9]_PORT_B_address_reg = DFFE(T1_q_a[9]_PORT_B_address, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_write_enable = GND;
T1_q_a[9]_PORT_A_write_enable_reg = DFFE(T1_q_a[9]_PORT_A_write_enable, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_write_enable = U1L53;
T1_q_a[9]_PORT_B_write_enable_reg = DFFE(T1_q_a[9]_PORT_B_write_enable, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[9]_clock_1 = GLOBAL(A1L5);
T1_q_a[9]_PORT_A_data_out = MEMORY(T1_q_a[9]_PORT_A_data_in_reg, T1_q_a[9]_PORT_B_data_in_reg, T1_q_a[9]_PORT_A_address_reg, T1_q_a[9]_PORT_B_address_reg, T1_q_a[9]_PORT_A_write_enable_reg, T1_q_a[9]_PORT_B_write_enable_reg, , , T1_q_a[9]_clock_0, T1_q_a[9]_clock_1, , , , );
T1_q_a[9]_PORT_A_data_out_reg = DFFE(T1_q_a[9]_PORT_A_data_out, T1_q_a[9]_clock_0, , , );
T1_q_a[0] = T1_q_a[9]_PORT_A_data_out_reg[3];

--T1_q_a[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[2] at M4K_X13_Y8
T1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_a[9]_PORT_A_data_in_reg = DFFE(T1_q_a[9]_PORT_A_data_in, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[9], U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[0]);
T1_q_a[9]_PORT_B_data_in_reg = DFFE(T1_q_a[9]_PORT_B_data_in, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[9]_PORT_A_address_reg = DFFE(T1_q_a[9]_PORT_A_address, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[9]_PORT_B_address_reg = DFFE(T1_q_a[9]_PORT_B_address, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_write_enable = GND;
T1_q_a[9]_PORT_A_write_enable_reg = DFFE(T1_q_a[9]_PORT_A_write_enable, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_write_enable = U1L53;
T1_q_a[9]_PORT_B_write_enable_reg = DFFE(T1_q_a[9]_PORT_B_write_enable, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[9]_clock_1 = GLOBAL(A1L5);
T1_q_a[9]_PORT_A_data_out = MEMORY(T1_q_a[9]_PORT_A_data_in_reg, T1_q_a[9]_PORT_B_data_in_reg, T1_q_a[9]_PORT_A_address_reg, T1_q_a[9]_PORT_B_address_reg, T1_q_a[9]_PORT_A_write_enable_reg, T1_q_a[9]_PORT_B_write_enable_reg, , , T1_q_a[9]_clock_0, T1_q_a[9]_clock_1, , , , );
T1_q_a[9]_PORT_A_data_out_reg = DFFE(T1_q_a[9]_PORT_A_data_out, T1_q_a[9]_clock_0, , , );
T1_q_a[2] = T1_q_a[9]_PORT_A_data_out_reg[2];

--T1_q_a[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[4] at M4K_X13_Y8
T1_q_a[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_a[9]_PORT_A_data_in_reg = DFFE(T1_q_a[9]_PORT_A_data_in, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[9], U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[0]);
T1_q_a[9]_PORT_B_data_in_reg = DFFE(T1_q_a[9]_PORT_B_data_in, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[9]_PORT_A_address_reg = DFFE(T1_q_a[9]_PORT_A_address, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[9]_PORT_B_address_reg = DFFE(T1_q_a[9]_PORT_B_address, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_PORT_A_write_enable = GND;
T1_q_a[9]_PORT_A_write_enable_reg = DFFE(T1_q_a[9]_PORT_A_write_enable, T1_q_a[9]_clock_0, , , );
T1_q_a[9]_PORT_B_write_enable = U1L53;
T1_q_a[9]_PORT_B_write_enable_reg = DFFE(T1_q_a[9]_PORT_B_write_enable, T1_q_a[9]_clock_1, , , );
T1_q_a[9]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[9]_clock_1 = GLOBAL(A1L5);
T1_q_a[9]_PORT_A_data_out = MEMORY(T1_q_a[9]_PORT_A_data_in_reg, T1_q_a[9]_PORT_B_data_in_reg, T1_q_a[9]_PORT_A_address_reg, T1_q_a[9]_PORT_B_address_reg, T1_q_a[9]_PORT_A_write_enable_reg, T1_q_a[9]_PORT_B_write_enable_reg, , , T1_q_a[9]_clock_0, T1_q_a[9]_clock_1, , , , );
T1_q_a[9]_PORT_A_data_out_reg = DFFE(T1_q_a[9]_PORT_A_data_out, T1_q_a[9]_clock_0, , , );
T1_q_a[4] = T1_q_a[9]_PORT_A_data_out_reg[1];

--T1_q_b[0] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[0] at M4K_X13_Y8
T1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_b[9]_PORT_A_data_in_reg = DFFE(T1_q_b[9]_PORT_A_data_in, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[9], U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[0]);
T1_q_b[9]_PORT_B_data_in_reg = DFFE(T1_q_b[9]_PORT_B_data_in, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[9]_PORT_A_address_reg = DFFE(T1_q_b[9]_PORT_A_address, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[9]_PORT_B_address_reg = DFFE(T1_q_b[9]_PORT_B_address, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_write_enable = GND;
T1_q_b[9]_PORT_A_write_enable_reg = DFFE(T1_q_b[9]_PORT_A_write_enable, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_write_enable = U1L53;
T1_q_b[9]_PORT_B_write_enable_reg = DFFE(T1_q_b[9]_PORT_B_write_enable, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[9]_clock_1 = GLOBAL(A1L5);
T1_q_b[9]_PORT_B_data_out = MEMORY(T1_q_b[9]_PORT_A_data_in_reg, T1_q_b[9]_PORT_B_data_in_reg, T1_q_b[9]_PORT_A_address_reg, T1_q_b[9]_PORT_B_address_reg, T1_q_b[9]_PORT_A_write_enable_reg, T1_q_b[9]_PORT_B_write_enable_reg, , , T1_q_b[9]_clock_0, T1_q_b[9]_clock_1, , , , );
T1_q_b[0] = T1_q_b[9]_PORT_B_data_out[3];

--T1_q_b[2] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[2] at M4K_X13_Y8
T1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_b[9]_PORT_A_data_in_reg = DFFE(T1_q_b[9]_PORT_A_data_in, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[9], U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[0]);
T1_q_b[9]_PORT_B_data_in_reg = DFFE(T1_q_b[9]_PORT_B_data_in, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[9]_PORT_A_address_reg = DFFE(T1_q_b[9]_PORT_A_address, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[9]_PORT_B_address_reg = DFFE(T1_q_b[9]_PORT_B_address, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_write_enable = GND;
T1_q_b[9]_PORT_A_write_enable_reg = DFFE(T1_q_b[9]_PORT_A_write_enable, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_write_enable = U1L53;
T1_q_b[9]_PORT_B_write_enable_reg = DFFE(T1_q_b[9]_PORT_B_write_enable, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[9]_clock_1 = GLOBAL(A1L5);
T1_q_b[9]_PORT_B_data_out = MEMORY(T1_q_b[9]_PORT_A_data_in_reg, T1_q_b[9]_PORT_B_data_in_reg, T1_q_b[9]_PORT_A_address_reg, T1_q_b[9]_PORT_B_address_reg, T1_q_b[9]_PORT_A_write_enable_reg, T1_q_b[9]_PORT_B_write_enable_reg, , , T1_q_b[9]_clock_0, T1_q_b[9]_clock_1, , , , );
T1_q_b[2] = T1_q_b[9]_PORT_B_data_out[2];

--T1_q_b[4] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[4] at M4K_X13_Y8
T1_q_b[9]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_b[9]_PORT_A_data_in_reg = DFFE(T1_q_b[9]_PORT_A_data_in, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[9], U1_ram_rom_data_reg[4], U1_ram_rom_data_reg[2], U1_ram_rom_data_reg[0]);
T1_q_b[9]_PORT_B_data_in_reg = DFFE(T1_q_b[9]_PORT_B_data_in, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[9]_PORT_A_address_reg = DFFE(T1_q_b[9]_PORT_A_address, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[9]_PORT_B_address_reg = DFFE(T1_q_b[9]_PORT_B_address, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_PORT_A_write_enable = GND;
T1_q_b[9]_PORT_A_write_enable_reg = DFFE(T1_q_b[9]_PORT_A_write_enable, T1_q_b[9]_clock_0, , , );
T1_q_b[9]_PORT_B_write_enable = U1L53;
T1_q_b[9]_PORT_B_write_enable_reg = DFFE(T1_q_b[9]_PORT_B_write_enable, T1_q_b[9]_clock_1, , , );
T1_q_b[9]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[9]_clock_1 = GLOBAL(A1L5);
T1_q_b[9]_PORT_B_data_out = MEMORY(T1_q_b[9]_PORT_A_data_in_reg, T1_q_b[9]_PORT_B_data_in_reg, T1_q_b[9]_PORT_A_address_reg, T1_q_b[9]_PORT_B_address_reg, T1_q_b[9]_PORT_A_write_enable_reg, T1_q_b[9]_PORT_B_write_enable_reg, , , T1_q_b[9]_clock_0, T1_q_b[9]_clock_1, , , , );
T1_q_b[4] = T1_q_b[9]_PORT_B_data_out[1];


--T1_q_a[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[8] at M4K_X13_Y9
--RAM Block Operation Mode: True Dual-Port
--Port A Depth: 1024, Port A Width: 4, Port B Depth: 1024, Port B Width: 4
--Port A Logical Depth: 1024, Port A Logical Width: 10, Port B Logical Depth: 1024, Port B Logical Width: 10
--Port A Input: Registered, Port A Output: Registered, Port B Input: Registered, Port B Output: Un-registered
T1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_a[8]_PORT_A_data_in_reg = DFFE(T1_q_a[8]_PORT_A_data_in, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[1]);
T1_q_a[8]_PORT_B_data_in_reg = DFFE(T1_q_a[8]_PORT_B_data_in, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[8]_PORT_A_address_reg = DFFE(T1_q_a[8]_PORT_A_address, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[8]_PORT_B_address_reg = DFFE(T1_q_a[8]_PORT_B_address, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_write_enable = GND;
T1_q_a[8]_PORT_A_write_enable_reg = DFFE(T1_q_a[8]_PORT_A_write_enable, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_write_enable = U1L53;
T1_q_a[8]_PORT_B_write_enable_reg = DFFE(T1_q_a[8]_PORT_B_write_enable, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[8]_clock_1 = GLOBAL(A1L5);
T1_q_a[8]_PORT_A_data_out = MEMORY(T1_q_a[8]_PORT_A_data_in_reg, T1_q_a[8]_PORT_B_data_in_reg, T1_q_a[8]_PORT_A_address_reg, T1_q_a[8]_PORT_B_address_reg, T1_q_a[8]_PORT_A_write_enable_reg, T1_q_a[8]_PORT_B_write_enable_reg, , , T1_q_a[8]_clock_0, T1_q_a[8]_clock_1, , , , );
T1_q_a[8]_PORT_A_data_out_reg = DFFE(T1_q_a[8]_PORT_A_data_out, T1_q_a[8]_clock_0, , , );
T1_q_a[8] = T1_q_a[8]_PORT_A_data_out_reg[0];

--T1_q_b[8] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_b[8] at M4K_X13_Y9
T1_q_b[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_b[8]_PORT_A_data_in_reg = DFFE(T1_q_b[8]_PORT_A_data_in, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[1]);
T1_q_b[8]_PORT_B_data_in_reg = DFFE(T1_q_b[8]_PORT_B_data_in, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_b[8]_PORT_A_address_reg = DFFE(T1_q_b[8]_PORT_A_address, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_b[8]_PORT_B_address_reg = DFFE(T1_q_b[8]_PORT_B_address, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_PORT_A_write_enable = GND;
T1_q_b[8]_PORT_A_write_enable_reg = DFFE(T1_q_b[8]_PORT_A_write_enable, T1_q_b[8]_clock_0, , , );
T1_q_b[8]_PORT_B_write_enable = U1L53;
T1_q_b[8]_PORT_B_write_enable_reg = DFFE(T1_q_b[8]_PORT_B_write_enable, T1_q_b[8]_clock_1, , , );
T1_q_b[8]_clock_0 = GLOBAL(J1_clock0);
T1_q_b[8]_clock_1 = GLOBAL(A1L5);
T1_q_b[8]_PORT_B_data_out = MEMORY(T1_q_b[8]_PORT_A_data_in_reg, T1_q_b[8]_PORT_B_data_in_reg, T1_q_b[8]_PORT_A_address_reg, T1_q_b[8]_PORT_B_address_reg, T1_q_b[8]_PORT_A_write_enable_reg, T1_q_b[8]_PORT_B_write_enable_reg, , , T1_q_b[8]_clock_0, T1_q_b[8]_clock_1, , , , );
T1_q_b[8] = T1_q_b[8]_PORT_B_data_out[0];

--T1_q_a[1] is sin_rom:u3|altsyncram:altsyncram_component|altsyncram_cvr:auto_generated|altsyncram_2q92:altsyncram1|q_a[1] at M4K_X13_Y9
T1_q_a[8]_PORT_A_data_in = BUS(VCC, VCC, VCC, VCC);
T1_q_a[8]_PORT_A_data_in_reg = DFFE(T1_q_a[8]_PORT_A_data_in, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_data_in = BUS(U1_ram_rom_data_reg[8], U1_ram_rom_data_reg[7], U1_ram_rom_data_reg[5], U1_ram_rom_data_reg[1]);
T1_q_a[8]_PORT_B_data_in_reg = DFFE(T1_q_a[8]_PORT_B_data_in, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_address = BUS(G1_dout[0], G1_dout[1], G1_dout[2], G1_dout[3], G1_dout[4], G1_dout[5], G1_dout[6], G1_dout[7], G1_dout[8], G1_dout[9]);
T1_q_a[8]_PORT_A_address_reg = DFFE(T1_q_a[8]_PORT_A_address, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_address = BUS(W1_safe_q[0], W1_safe_q[1], W1_safe_q[2], W1_safe_q[3], W1_safe_q[4], W1_safe_q[5], W1_safe_q[6], W1_safe_q[7], W1_safe_q[8], W1_safe_q[9]);
T1_q_a[8]_PORT_B_address_reg = DFFE(T1_q_a[8]_PORT_B_address, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_PORT_A_write_enable = GND;
T1_q_a[8]_PORT_A_write_enable_reg = DFFE(T1_q_a[8]_PORT_A_write_enable, T1_q_a[8]_clock_0, , , );
T1_q_a[8]_PORT_B_write_enable = U1L53;
T1_q_a[8]_PORT_B_write_enable_reg = DFFE(T1_q_a[8]_PORT_B_write_enable, T1_q_a[8]_clock_1, , , );
T1_q_a[8]_clock_0 = GLOBAL(J1_clock0);
T1_q_a[8]_clock_1 = GLOBAL(A1L5);