dds_vhdl.map.rpt

基于fpga的正弦波发生器设计

;       |sld_dffex:\GEN_SHADOW_IRF:1:S_IRF|                              ; 5 (5)       ; 5            ; 0           ; 0    ; 0    ; 0            ; 0 (0)        ; 5 (5)             ; 0 (0)            ; 0 (0)           ; 0 (0)      ; |dds_vhdl|sld_hub:sld_hub_inst|sld_dffex:\GEN_SHADOW_IRF:1:S_IRF                                                                                                    ;
;       |sld_jtag_state_machine:jtag_state_machine|                      ; 21 (21)     ; 19           ; 0           ; 0    ; 0    ; 0            ; 2 (2)        ; 0 (0)             ; 19 (19)          ; 0 (0)           ; 0 (0)      ; |dds_vhdl|sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine                                                                                            ;
;       |sld_rom_sr:HUB_INFO_REG|                                        ; 21 (21)     ; 9            ; 0           ; 0    ; 0    ; 0            ; 12 (12)      ; 0 (0)             ; 9 (9)            ; 5 (5)           ; 0 (0)      ; |dds_vhdl|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG                                                                                                              ;
+------------------------------------------------------------------------+-------------+--------------+-------------+------+------+--------------+--------------+-------------------+------------------+-----------------+------------+---------------------------------------------------------------------------------------------------------------------------------------------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis RAM Summary                                                                                                                                                                                          ;
+------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+-------+------------+
; Name                                                                                                             ; Type ; Mode           ; Port A Depth ; Port A Width ; Port B Depth ; Port B Width ; Size  ; MIF        ;
+------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+-------+------------+
; sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1|ALTSYNCRAM ; AUTO ; True Dual Port ; 1024         ; 10           ; 1024         ; 10           ; 10240 ; ./romd.mif ;
+------------------------------------------------------------------------------------------------------------------+------+----------------+--------------+--------------+--------------+--------------+-------+------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 144   ;
; Number of registers using Synchronous Clear  ; 20    ;
; Number of registers using Synchronous Load   ; 10    ;
; Number of registers using Asynchronous Clear ; 94    ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 65    ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; sld_hub:sld_hub_inst|hub_tdo           ; 2       ;
; Total number of inverted registers = 1 ;         ;
+----------------------------------------+---------+


+---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Restructuring Statistics (Restructuring Performed)                                                                                                                                                                                                                                    ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output                                                                                                                                                          ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; 3:1                ; 5 bits    ; 10 LEs        ; 5 LEs                ; 5 LEs                  ; Yes        ; |dds_vhdl|sld_hub:sld_hub_inst|sld_dffex:IRSR|Q[0]                                                                                                                                  ;
; 5:1                ; 5 bits    ; 15 LEs        ; 5 LEs                ; 10 LEs                 ; Yes        ; |dds_vhdl|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|word_counter[0]                                                                                                              ;
; 20:1               ; 4 bits    ; 52 LEs        ; 32 LEs               ; 20 LEs                 ; Yes        ; |dds_vhdl|sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG|WORD_SR[0]                                                                                                                   ;
; 3:1                ; 10 bits   ; 20 LEs        ; 10 LEs               ; 10 LEs                 ; Yes        ; |dds_vhdl|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|ram_rom_data_reg[6]                                                   ;
; 5:1                ; 4 bits    ; 12 LEs        ; 4 LEs                ; 8 LEs                  ; Yes        ; |dds_vhdl|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|word_counter[0] ;
; 16:1               ; 4 bits    ; 40 LEs        ; 28 LEs               ; 12 LEs                 ; Yes        ; |dds_vhdl|sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr|WORD_SR[0]      ;
+--------------------+-----------+---------------+----------------------+------------------------+------------+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+


+------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|altsyncram_eui2:altsyncram1 ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+
; Assignment                      ; Value              ; From ; To                                                             ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+
; OPTIMIZE_POWER_DURING_SYNTHESIS ; NORMAL_COMPILATION ; -    ; -                                                              ;
+---------------------------------+--------------------+------+----------------------------------------------------------------+


+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Source assignments for sin_rom:u3|altsyncram:altsyncram_component|altsyncram_o351:auto_generated|sld_mod_ram_rom:mgl_prim2|sld_rom_sr:\ram_rom_logic_gen:no_name_gen:info_rom_sr ;
+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; Assignment           ; Value ; From ; To                                                                                                                                         ;
+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                                                                                                                                          ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[0]                                                                                                                            ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[1]                                                                                                                            ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[2]                                                                                                                            ;
; POWER_UP_LEVEL       ; Low   ; -    ; word_counter[3]                                                                                                                            ;
+----------------------+-------+------+--------------------------------------------------------------------------------------------------------------------------------------------+


+----------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst              ;
+------------------------------+-------+------+------------+
; Assignment                   ; Value ; From ; To         ;
+------------------------------+-------+------+------------+
; IGNORE_LCELL_BUFFERS         ; OFF   ; -    ; -          ;
; REMOVE_REDUNDANT_LOGIC_CELLS ; OFF   ; -    ; -          ;
; NOT_GATE_PUSH_BACK           ; OFF   ; -    ; CLR_SIGNAL ;
; POWER_UP_LEVEL               ; LOW   ; -    ; CLR_SIGNAL ;
+------------------------------+-------+------+------------+


+---------------------------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_jtag_state_machine:jtag_state_machine ;
+----------------+-------+------+-------------------------------------------------------+
; Assignment     ; Value ; From ; To                                                    ;
+----------------+-------+------+-------------------------------------------------------+
; POWER_UP_LEVEL ; Low   ; -    ; state[0]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[1]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[2]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[3]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[4]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[5]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[6]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[7]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[8]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[9]                                              ;
; POWER_UP_LEVEL ; Low   ; -    ; state[10]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[11]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[12]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[13]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[14]                                             ;
; POWER_UP_LEVEL ; Low   ; -    ; state[15]                                             ;
+----------------+-------+------+-------------------------------------------------------+


+---------------------------------------------------------------------+
; Source assignments for sld_hub:sld_hub_inst|sld_rom_sr:HUB_INFO_REG ;
+----------------------+-------+------+-------------------------------+
; Assignment           ; Value ; From ; To                            ;
+----------------------+-------+------+-------------------------------+
; AUTO_ROM_RECOGNITION ; OFF   ; -    ; -                             ;