ir.fit.qmsg

利用Verilig编写CPLD读写EEPROM（74LC21）程序

{ "Info" "IFYGR_FYGR_NO_REGS_IN_IOS_FOOTER" "" "Info: Finished processing fast register assignments" {  } {  } 0}
{ "Info" "IFSAC_FSAC_FINISH_LUT_PACKING" "" "Info: Finished moving registers into LUTs" {  } {  } 0}
{ "Info" "IFSAC_FSAC_REGISTER_PACKING_FINISH_REGPACKING_INFO" "" "Info: Finished register packing" {  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement " "Info: Statistics of I/O pins that need to be placed that use the same VCCIO and VREF, before I/O pin placement" { { "Info" "IFSAC_FSAC_SINGLE_IOC_GROUP_STATISTICS" "8 unused 3.30 1 7 0 " "Info: Number of I/O pins in group: 8 (unused VREF, 3.30 VCCIO, 1 input, 7 output, 0 bidirectional)" { { "Info" "IFSAC_FSAC_IO_STDS_IN_IOC_GROUP" "LVTTL. " "Info: I/O standards used: LVTTL." {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFSAC_FSAC_IO_STATS_BEFORE_AFTER_PLACEMENT" "before " "Info: I/O bank details before I/O pin placement" { { "Info" "IFSAC_FSAC_IO_BANK_PIN_GROUP_STATISTICS" "I/O banks " "Info: Statistics of I/O banks" { { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "1 does not use 3.30V 2 36 " "Info: I/O bank number 1 does not use VREF pins and has 3.30V VCCIO pins. 2 total pin(s) used --  36 pins available" {  } {  } 0} { "Info" "IFSAC_FSAC_SINGLE_IO_BANK_STATISTICS" "2 does not use unused 0 42 " "Info: I/O bank number 2 does not use VREF pins and has unused VCCIO pins. 0 total pin(s) used --  42 pins available" {  } {  } 0}  } {  } 0}  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_START" "" "Info: Fitter placement preparation operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_PREP_END" "00:00:00 " "Info: Fitter placement preparation operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_START" "" "Info: Fitter placement operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_INFO_VPR_PLACEMENT_FINISH" "" "Info: Fitter placement was successful" {  } {  } 0}
{ "Info" "ITDB_FULL_ESTIMATED_DATA_PATH_RESULT" "6.027 ns pin pin " "Info: Estimated most critical path is pin to pin delay of 6.027 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns IRInput 1 PIN PIN_38 1 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_38; Fanout = 1; PIN Node = 'IRInput'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR_cmp.qrpt" Compiler "IR" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/IR/" "" "" { IRInput } "NODE_NAME" } "" } } { "IR.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/IR/IR.v" 8 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.573 ns) + CELL(2.322 ns) 6.027 ns LED\[0\] 2 PIN PIN_4 0 " "Info: 2: + IC(2.573 ns) + CELL(2.322 ns) = 6.027 ns; Loc. = PIN_4; Fanout = 0; PIN Node = 'LED\[0\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR_cmp.qrpt" Compiler "IR" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/IR/" "" "4.895 ns" { IRInput LED[0] } "NODE_NAME" } "" } } { "IR.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/IR/IR.v" 10 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns 57.31 % " "Info: Total cell delay = 3.454 ns ( 57.31 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.573 ns 42.69 % " "Info: Total interconnect delay = 2.573 ns ( 42.69 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR_cmp.qrpt" Compiler "IR" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/IR/db/IR.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/IR/" "" "6.027 ns" { IRInput LED[0] } "NODE_NAME" } "" } }  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_PLACEMENT_END" "00:00:00 " "Info: Fitter placement operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_START" "" "Info: Fitter routing operations beginning" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_FITTER_ROUTING_END" "00:00:00 " "Info: Fitter routing operations ending: elapsed time is 00:00:00" {  } {  } 0}
{ "Info" "IFITAPI_FITAPI_VPR_AUTO_FIT_ENABLED_AND_NOT_USED" "" "Info: Fitter performed an Auto Fit compilation.  No optimizations were skipped because the design's timing and/or routability requirements required full optimization" {  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Fitter 0 s 0 s Quartus II " "Info: Quartus II Fitter was successful. 0 errors, 0 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Wed May 30 21:56:17 2007 " "Info: Processing ended: Wed May 30 21:56:17 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}