pwmtest.tan.rpt

利用VHDL实现CPLD（EMP240T100C5）的PWM输出

; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Timing Analyzer
    Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
    Info: Processing started: Thu May 31 18:54:44 2007
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off pwmtest -c pwmtest
Info: Started post-fitting delay annotation
Info: Delay annotation completed successfully
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clkfast" is an undefined clock
Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "pwm_clkdiv[7]" as buffer
    Info: Detected ripple clock "pwm_fpga:pwm_control|rco_int" as buffer
Info: Clock "clkfast" has Internal fmax of 45.1 MHz between source register "pwm_fpga:pwm_control|pwm" and destination register "pwm_fpga:pwm_control|cnt_out_int[5]" (period= 22.172 ns)
    Info: + Longest register to register delay is 5.732 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N3; Fanout = 5; REG Node = 'pwm_fpga:pwm_control|pwm'
        Info: 2: + IC(0.924 ns) + CELL(0.200 ns) = 1.124 ns; Loc. = LC_X7_Y4_N2; Fanout = 10; COMB Node = 'pwm_fpga:pwm_control|process1~134'
        Info: 3: + IC(2.465 ns) + CELL(0.200 ns) = 3.789 ns; Loc. = LC_X5_Y4_N7; Fanout = 1; COMB Node = 'pwm_fpga:pwm_control|cnt_out_int~3730'
        Info: 4: + IC(0.700 ns) + CELL(1.243 ns) = 5.732 ns; Loc. = LC_X5_Y4_N9; Fanout = 4; REG Node = 'pwm_fpga:pwm_control|cnt_out_int[5]'
        Info: Total cell delay = 1.643 ns ( 28.66 % )
        Info: Total interconnect delay = 4.089 ns ( 71.34 % )
    Info: - Smallest clock skew is -4.645 ns
        Info: + Shortest clock path from clock "clkfast" to destination register is 7.373 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv[7]'
            Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.373 ns; Loc. = LC_X5_Y4_N9; Fanout = 4; REG Node = 'pwm_fpga:pwm_control|cnt_out_int[5]'
            Info: Total cell delay = 3.375 ns ( 45.78 % )
            Info: Total interconnect delay = 3.998 ns ( 54.22 % )
        Info: - Longest clock path from clock "clkfast" to source register is 12.018 ns
            Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'
            Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv[7]'
            Info: 3: + IC(2.731 ns) + CELL(1.294 ns) = 7.749 ns; Loc. = LC_X5_Y3_N3; Fanout = 12; REG Node = 'pwm_fpga:pwm_control|rco_int'
            Info: 4: + IC(3.351 ns) + CELL(0.918 ns) = 12.018 ns; Loc. = LC_X7_Y4_N3; Fanout = 5; REG Node = 'pwm_fpga:pwm_control|pwm'
            Info: Total cell delay = 4.669 ns ( 38.85 % )
            Info: Total interconnect delay = 7.349 ns ( 61.15 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Micro setup delay of destination is 0.333 ns
    Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two
Info: tsu for register "pwm_fpga:pwm_control|reg_out[0]" (data pin = "SW[0]", clock pin = "clkfast") is -3.318 ns
    Info: + Longest pin to register delay is 3.722 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 2; PIN Node = 'SW[0]'
        Info: 2: + IC(2.310 ns) + CELL(0.280 ns) = 3.722 ns; Loc. = LC_X2_Y4_N6; Fanout = 1; REG Node = 'pwm_fpga:pwm_control|reg_out[0]'
        Info: Total cell delay = 1.412 ns ( 37.94 % )
        Info: Total interconnect delay = 2.310 ns ( 62.06 % )
    Info: + Micro setup delay of destination is 0.333 ns
    Info: - Shortest clock path from clock "clkfast" to destination register is 7.373 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv[7]'
        Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.373 ns; Loc. = LC_X2_Y4_N6; Fanout = 1; REG Node = 'pwm_fpga:pwm_control|reg_out[0]'
        Info: Total cell delay = 3.375 ns ( 45.78 % )
        Info: Total interconnect delay = 3.998 ns ( 54.22 % )
Info: tco from clock "clkfast" to destination pin "pwm_out" through register "pwm_fpga:pwm_control|pwm" is 15.511 ns
    Info: + Longest clock path from clock "clkfast" to source register is 12.018 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv[7]'
        Info: 3: + IC(2.731 ns) + CELL(1.294 ns) = 7.749 ns; Loc. = LC_X5_Y3_N3; Fanout = 12; REG Node = 'pwm_fpga:pwm_control|rco_int'
        Info: 4: + IC(3.351 ns) + CELL(0.918 ns) = 12.018 ns; Loc. = LC_X7_Y4_N3; Fanout = 5; REG Node = 'pwm_fpga:pwm_control|pwm'
        Info: Total cell delay = 4.669 ns ( 38.85 % )
        Info: Total interconnect delay = 7.349 ns ( 61.15 % )
    Info: + Micro clock to output delay of source is 0.376 ns
    Info: + Longest register to pin delay is 3.117 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N3; Fanout = 5; REG Node = 'pwm_fpga:pwm_control|pwm'
        Info: 2: + IC(0.795 ns) + CELL(2.322 ns) = 3.117 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'pwm_out'
        Info: Total cell delay = 2.322 ns ( 74.49 % )
        Info: Total interconnect delay = 0.795 ns ( 25.51 % )
Info: Longest tpd from source pin "SW[7]" to destination pin "LED[7]" is 6.271 ns
    Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_37; Fanout = 2; PIN Node = 'SW[7]'
    Info: 2: + IC(2.817 ns) + CELL(2.322 ns) = 6.271 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'LED[7]'
    Info: Total cell delay = 3.454 ns ( 55.08 % )
    Info: Total interconnect delay = 2.817 ns ( 44.92 % )
Info: th for register "pwm_fpga:pwm_control|reg_out[4]" (data pin = "SW[4]", clock pin = "clkfast") is 4.016 ns
    Info: + Longest clock path from clock "clkfast" to destination register is 7.373 ns
        Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'
        Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv[7]'
        Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.373 ns; Loc. = LC_X3_Y3_N0; Fanout = 1; REG Node = 'pwm_fpga:pwm_control|reg_out[4]'
        Info: Total cell delay = 3.375 ns ( 45.78 % )
        Info: Total interconnect delay = 3.998 ns ( 54.22 % )
    Info: + Micro hold delay of destination is 0.221 ns
    Info: - Shortest pin to register delay is 3.578 ns
        Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_34; Fanout = 2; PIN Node = 'SW[4]'
        Info: 2: + IC(2.166 ns) + CELL(0.280 ns) = 3.578 ns; Loc. = LC_X3_Y3_N0; Fanout = 1; REG Node = 'pwm_fpga:pwm_control|reg_out[4]'
        Info: Total cell delay = 1.412 ns ( 39.46 % )
        Info: Total interconnect delay = 2.166 ns ( 60.54 % )
Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Processing ended: Thu May 31 18:54:45 2007
    Info: Elapsed time: 00:00:02