pwmtest.v

来自「利用VHDL实现CPLD（EMP240T100C5）的PWM输出」· Verilog 代码 · 共 33 行

module pwmtest
	(
		SW,
		clkfast,
		pwm_out,
		LED,
		RST
	);

	input[7:0]	SW;
	input clkfast,RST;
	output	pwm_out;
	output[7:0] LED;


	// Wire Declaration

	// Integer Declaration
	reg[7:0] pwm_clkdiv;
	// Concurrent Assignment
	assign LED[7:0] = ~SW;
	always @(posedge clkfast)
	begin
		pwm_clkdiv <= pwm_clkdiv + 1;
	end

	// Always Construct
	pwm_fpga pwm_control(.clock(pwm_clkdiv[7]),
	.reset(RST),
	.Data_value(SW),
	.pwm(pwm_out));
endmodule