📄 pwmtest.fit.rpt
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; LAB clocks ; 15 / 32 ( 46 % ) ;
; LUT chains ; 7 / 216 ( 3 % ) ;
; Local interconnects ; 70 / 888 ( 7 % ) ;
; R4s ; 41 / 704 ( 5 % ) ;
+----------------------------+------------------+
+---------------------------------------------------------------------------+
; LAB Logic Elements ;
+--------------------------------------------+------------------------------+
; Number of Logic Elements (Average = 4.90) ; Number of LABs (Total = 10) ;
+--------------------------------------------+------------------------------+
; 1 ; 2 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 3 ;
+--------------------------------------------+------------------------------+
+-------------------------------------------------------------------+
; LAB-wide Signals ;
+------------------------------------+------------------------------+
; LAB-wide Signals (Average = 2.00) ; Number of LABs (Total = 10) ;
+------------------------------------+------------------------------+
; 1 Async. clear ; 7 ;
; 1 Async. load ; 2 ;
; 1 Clock ; 9 ;
; 1 Clock enable ; 1 ;
; 2 Clocks ; 1 ;
+------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Signals Sourced ;
+---------------------------------------------+------------------------------+
; Number of Signals Sourced (Average = 4.90) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 2 ;
; 2 ; 3 ;
; 3 ; 1 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 0 ;
; 8 ; 1 ;
; 9 ; 0 ;
; 10 ; 3 ;
+---------------------------------------------+------------------------------+
+--------------------------------------------------------------------------------+
; LAB Signals Sourced Out ;
+-------------------------------------------------+------------------------------+
; Number of Signals Sourced Out (Average = 3.20) ; Number of LABs (Total = 10) ;
+-------------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 3 ;
; 2 ; 4 ;
; 3 ; 0 ;
; 4 ; 0 ;
; 5 ; 0 ;
; 6 ; 1 ;
; 7 ; 1 ;
; 8 ; 1 ;
+-------------------------------------------------+------------------------------+
+----------------------------------------------------------------------------+
; LAB Distinct Inputs ;
+---------------------------------------------+------------------------------+
; Number of Distinct Inputs (Average = 6.90) ; Number of LABs (Total = 10) ;
+---------------------------------------------+------------------------------+
; 0 ; 0 ;
; 1 ; 1 ;
; 2 ; 0 ;
; 3 ; 2 ;
; 4 ; 3 ;
; 5 ; 0 ;
; 6 ; 0 ;
; 7 ; 1 ;
; 8 ; 0 ;
; 9 ; 0 ;
; 10 ; 0 ;
; 11 ; 0 ;
; 12 ; 0 ;
; 13 ; 2 ;
; 14 ; 0 ;
; 15 ; 0 ;
; 16 ; 0 ;
; 17 ; 1 ;
+---------------------------------------------+------------------------------+
+-----------------+
; Fitter Messages ;
+-----------------+
Info: *******************************************************************
Info: Running Quartus II Fitter
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
Info: Processing started: Thu May 31 18:54:38 2007
Info: Command: quartus_fit --read_settings_files=off --write_settings_files=off pwmtest -c pwmtest
Info: Selected device EPM240T100C5 for design "pwmtest"
Info: Fitter is performing an Auto Fit compilation, which may decrease Fitter effort to reduce compilation time
Info: Device migration not selected. If you intend to use device migration later, you may need to change the pin assignments as they may be incompatible with other devices.
Info: Device EPM240T100I5 is compatible
Info: Device EPM570T100C5 is compatible
Info: Device EPM570T100I5 is compatible
Info: Timing requirements not specified -- optimizing circuit to achieve the following default global requirements
Info: Assuming a global fmax requirement of 1000 MHz
Info: Assuming a global tsu requirement of 2.0 ns
Info: Assuming a global tco requirement of 1.0 ns
Info: Assuming a global tpd requirement of 1.0 ns
Info: Performing register packing on registers with non-logic cell location assignments
Info: Completed register packing on registers with non-logic cell location assignments
Info: Completed User Assigned Global Signals Promotion Operation
Info: Automatically promoted signal "clkfast" to use Global clock in PIN 12
Info: Automatically promoted some destinations of signal "pwm_clkdiv[7]" to use Global clock
Info: Destination "pwm_clkdiv[7]" may be non-global or may not use global clock
Info: Automatically promoted signal "RST" to use Global clock
Info: Pin "RST" drives global clock, but is not placed in a dedicated clock pin position
Info: Automatically promoted some destinations of signal "pwm_fpga:pwm_control|rco_int" to use Global clock
Info: Destination "pwm_fpga:pwm_control|process1~133" may be non-global or may not use global clock
Info: Destination "pwm_fpga:pwm_control|process1~134" may be non-global or may not use global clock
Info: Destination "pwm_fpga:pwm_control|cnt_out_int~3739" may be non-global or may not use global clock
Info: Completed Auto Global Promotion Operation
Info: Starting register packing
Info: Fitter is using Normal packing mode for logic elements with Auto setting for Auto Packed Registers logic option
Info: Moving registers into LUTs to improve timing and density
Info: Started processing fast register assignments
Info: Finished processing fast register assignments
Info: Finished moving registers into LUTs
Info: Finished register packing
Info: Fitter placement preparation operations beginning
Info: Fitter placement preparation operations ending: elapsed time is 00:00:00
Info: Fitter placement operations beginning
Info: Fitter placement was successful
Info: Estimated most critical path is register to pin delay of 2.900 ns
Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LAB_X7_Y4; Fanout = 5; REG Node = 'pwm_fpga:pwm_control|pwm'
Info: 2: + IC(0.578 ns) + CELL(2.322 ns) = 2.900 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'pwm_out'
Info: Total cell delay = 2.322 ns ( 80.07 % )
Info: Total interconnect delay = 0.578 ns ( 19.93 % )
Info: Fitter placement operations ending: elapsed time is 00:00:00
Info: Fitter routing operations beginning
Info: Fitter routing operations ending: elapsed time is 00:00:00
Info: Fitter performed an Auto Fit compilation. No optimizations were skipped because the design's timing and/or routability requirements required full optimization
Info: Quartus II Fitter was successful. 0 errors, 0 warnings
Info: Processing ended: Thu May 31 18:54:40 2007
Info: Elapsed time: 00:00:03
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