pwmtest.map.qmsg

利用VHDL实现CPLD（EMP240T100C5）的PWM输出

{ "Info" "IQEXE_SEPARATOR" "" "Info: *******************************************************************" {  } {  } 3}
{ "Info" "IQEXE_START_BANNER_PRODUCT" "Analysis & Synthesis Quartus II " "Info: Running Quartus II Analysis & Synthesis" { { "Info" "IQEXE_START_BANNER_VERSION" "Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version " "Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version" {  } {  } 0} { "Info" "IQEXE_START_BANNER_TIME" "Thu May 31 18:54:32 2007 " "Info: Processing started: Thu May 31 18:54:32 2007" {  } {  } 0}  } {  } 4}
{ "Info" "IQEXE_START_BANNER_COMMANDLINE" "quartus_map --read_settings_files=on --write_settings_files=off pwmtest -c pwmtest " "Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pwmtest -c pwmtest" {  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwm_fpga.vhdl 2 1 " "Info: Found 2 design units, including 1 entities, in source file pwm_fpga.vhdl" { { "Info" "ISGN_DESIGN_UNIT_NAME" "1 pwm_fpga-arch_pwm " "Info: Found design unit 1: pwm_fpga-arch_pwm" {  } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 11 -1 0 } }  } 0} { "Info" "ISGN_ENTITY_NAME" "1 pwm_fpga " "Info: Found entity 1: pwm_fpga" {  } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 5 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_NUM_OF_DESIGN_UNITS_AND_ENTITIES" "pwmtest.v 1 1 " "Info: Found 1 design units, including 1 entities, in source file pwmtest.v" { { "Info" "ISGN_ENTITY_NAME" "1 pwmtest " "Info: Found entity 1: pwmtest" {  } { { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 1 -1 0 } }  } 0}  } {  } 0}
{ "Info" "ISGN_START_ELABORATION_TOP" "pwmtest " "Info: Elaborating entity \"pwmtest\" for the top level hierarchy" {  } {  } 0}
{ "Warning" "WVRFX_VERI_EXPRESSION_TRUNCATED_TO_FIT" "32 8 pwmtest.v(24) " "Warning: Verilog HDL assignment warning at pwmtest.v(24): truncated value with size 32 to match size of target (8)" {  } { { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 24 0 0 } }  } 0}
{ "Info" "ISGN_START_ELABORATION_HIERARCHY" "pwm_fpga pwm_fpga:pwm_control " "Info: Elaborating entity \"pwm_fpga\" for hierarchy \"pwm_fpga:pwm_control\"" {  } { { "pwmtest.v" "pwm_control" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 31 -1 0 } }  } 0}
{ "Warning" "WVRFX_VHDL_SHOULD_BE_ON_THE_PROCESSES_SENSITIVITY_LIST" "pwm_int pwm_fpga.vhdl(77) " "Warning: VHDL Process Statement warning at pwm_fpga.vhdl(77): signal \"pwm_int\" is read inside the Process Statement but isn't in the Process Statement's sensivitity list" {  } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 77 0 0 } }  } 0}
{ "Info" "IFTM_FTM_PRESET_POWER_UP" "" "Info: Registers with preset signals will power-up high" {  } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 14 -1 0 } }  } 0}
{ "Info" "ISCL_SCL_TM_SUMMARY" "70 " "Info: Implemented 70 device resources after synthesis - the final resource count might be different" { { "Info" "ISCL_SCL_TM_IPINS" "10 " "Info: Implemented 10 input pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_OPINS" "9 " "Info: Implemented 9 output pins" {  } {  } 0} { "Info" "ISCL_SCL_TM_LCELLS" "51 " "Info: Implemented 51 logic cells" {  } {  } 0}  } {  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Analysis & Synthesis 0 s 2 s Quartus II " "Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 18:54:36 2007 " "Info: Processing ended: Thu May 31 18:54:36 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:04 " "Info: Elapsed time: 00:00:04" {  } {  } 0}  } {  } 0}