pwmtest.tan.qmsg

利用VHDL实现CPLD（EMP240T100C5）的PWM输出

{ "Info" "ITDB_FULL_TPD_RESULT" "SW\[7\] LED\[7\] 6.271 ns Longest " "Info: Longest tpd from source pin \"SW\[7\]\" to destination pin \"LED\[7\]\" is 6.271 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SW\[7\] 1 PIN PIN_37 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_37; Fanout = 2; PIN Node = 'SW\[7\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { SW[7] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.817 ns) + CELL(2.322 ns) 6.271 ns LED\[7\] 2 PIN PIN_17 0 " "Info: 2: + IC(2.817 ns) + CELL(2.322 ns) = 6.271 ns; Loc. = PIN_17; Fanout = 0; PIN Node = 'LED\[7\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "5.139 ns" { SW[7] LED[7] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 13 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.454 ns 55.08 % " "Info: Total cell delay = 3.454 ns ( 55.08 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.817 ns 44.92 % " "Info: Total interconnect delay = 2.817 ns ( 44.92 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "6.271 ns" { SW[7] LED[7] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "6.271 ns" { SW[7] SW[7]~combout LED[7] } { 0.000ns 0.000ns 2.817ns } { 0.000ns 1.132ns 2.322ns } } }  } 0}
{ "Info" "ITDB_TH_RESULT" "pwm_fpga:pwm_control\|reg_out\[4\] SW\[4\] clkfast 4.016 ns register " "Info: th for register \"pwm_fpga:pwm_control\|reg_out\[4\]\" (data pin = \"SW\[4\]\", clock pin = \"clkfast\") is 4.016 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkfast destination 7.373 ns + Longest register " "Info: + Longest clock path from clock \"clkfast\" to destination register is 7.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkfast 1 CLK PIN_12 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { clkfast } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 11 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns pwm_clkdiv\[7\] 2 REG LC_X2_Y3_N7 18 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv\[7\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "2.561 ns" { clkfast pwm_clkdiv[7] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 19 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(0.918 ns) 7.373 ns pwm_fpga:pwm_control\|reg_out\[4\] 3 REG LC_X3_Y3_N0 1 " "Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.373 ns; Loc. = LC_X3_Y3_N0; Fanout = 1; REG Node = 'pwm_fpga:pwm_control\|reg_out\[4\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.649 ns" { pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[4] } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 45.78 % " "Info: Total cell delay = 3.375 ns ( 45.78 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.998 ns 54.22 % " "Info: Total interconnect delay = 3.998 ns ( 54.22 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "7.373 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.373 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[4] } { 0.000ns 0.000ns 1.267ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } }  } 0} { "Info" "ITDB_FULL_TH_DELAY" "0.221 ns + " "Info: + Micro hold delay of destination is 0.221 ns" {  } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.578 ns - Shortest pin register " "Info: - Shortest pin to register delay is 3.578 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SW\[4\] 1 PIN PIN_34 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_34; Fanout = 2; PIN Node = 'SW\[4\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { SW[4] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 10 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.166 ns) + CELL(0.280 ns) 3.578 ns pwm_fpga:pwm_control\|reg_out\[4\] 2 REG LC_X3_Y3_N0 1 " "Info: 2: + IC(2.166 ns) + CELL(0.280 ns) = 3.578 ns; Loc. = LC_X3_Y3_N0; Fanout = 1; REG Node = 'pwm_fpga:pwm_control\|reg_out\[4\]'" {  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "2.446 ns" { SW[4] pwm_fpga:pwm_control|reg_out[4] } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 12 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns 39.46 % " "Info: Total cell delay = 1.412 ns ( 39.46 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.166 ns 60.54 % " "Info: Total interconnect delay = 2.166 ns ( 60.54 % )" {  } {  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.578 ns" { SW[4] pwm_fpga:pwm_control|reg_out[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.578 ns" { SW[4] SW[4]~combout pwm_fpga:pwm_control|reg_out[4] } { 0.000ns 0.000ns 2.166ns } { 0.000ns 1.132ns 0.280ns } } }  } 0}  } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "7.373 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.373 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[4] } { 0.000ns 0.000ns 1.267ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.578 ns" { SW[4] pwm_fpga:pwm_control|reg_out[4] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.578 ns" { SW[4] SW[4]~combout pwm_fpga:pwm_control|reg_out[4] } { 0.000ns 0.000ns 2.166ns } { 0.000ns 1.132ns 0.280ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 2 s Quartus II " "Info: Quartus II Timing Analyzer was successful. 0 errors, 2 warnings" { { "Info" "IQEXE_END_BANNER_TIME" "Thu May 31 18:54:45 2007 " "Info: Processing ended: Thu May 31 18:54:45 2007" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}