📄 pwmtest.tan.qmsg
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{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "clkfast " "Info: Assuming node \"clkfast\" is an undefined clock" { } { { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 11 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "clkfast" } } } } } 0} } { } 0}
{ "Warning" "WTAN_RIPPLE_OR_GATED_CLOCKS_FOUND" "2 " "Warning: Found 2 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew" { { "Info" "ITAN_RIPPLE_CLK" "pwm_clkdiv\[7\] " "Info: Detected ripple clock \"pwm_clkdiv\[7\]\" as buffer" { } { { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 19 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pwm_clkdiv\[7\]" } } } } } 0} { "Info" "ITAN_RIPPLE_CLK" "pwm_fpga:pwm_control\|rco_int " "Info: Detected ripple clock \"pwm_fpga:pwm_control\|rco_int\" as buffer" { } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 14 -1 0 } } { "d:/altera/quartus50/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus50/bin/Assignment Editor.qase" 1 { { 0 "pwm_fpga:pwm_control\|rco_int" } } } } } 0} } { } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "clkfast register pwm_fpga:pwm_control\|pwm register pwm_fpga:pwm_control\|cnt_out_int\[5\] 45.1 MHz 22.172 ns Internal " "Info: Clock \"clkfast\" has Internal fmax of 45.1 MHz between source register \"pwm_fpga:pwm_control\|pwm\" and destination register \"pwm_fpga:pwm_control\|cnt_out_int\[5\]\" (period= 22.172 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "5.732 ns + Longest register register " "Info: + Longest register to register delay is 5.732 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm_fpga:pwm_control\|pwm 1 REG LC_X7_Y4_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N3; Fanout = 5; REG Node = 'pwm_fpga:pwm_control\|pwm'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.924 ns) + CELL(0.200 ns) 1.124 ns pwm_fpga:pwm_control\|process1~134 2 COMB LC_X7_Y4_N2 10 " "Info: 2: + IC(0.924 ns) + CELL(0.200 ns) = 1.124 ns; Loc. = LC_X7_Y4_N2; Fanout = 10; COMB Node = 'pwm_fpga:pwm_control\|process1~134'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "1.124 ns" { pwm_fpga:pwm_control|pwm pwm_fpga:pwm_control|process1~134 } "NODE_NAME" } "" } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.465 ns) + CELL(0.200 ns) 3.789 ns pwm_fpga:pwm_control\|cnt_out_int~3730 3 COMB LC_X5_Y4_N7 1 " "Info: 3: + IC(2.465 ns) + CELL(0.200 ns) = 3.789 ns; Loc. = LC_X5_Y4_N7; Fanout = 1; COMB Node = 'pwm_fpga:pwm_control\|cnt_out_int~3730'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "2.665 ns" { pwm_fpga:pwm_control|process1~134 pwm_fpga:pwm_control|cnt_out_int~3730 } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 13 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.700 ns) + CELL(1.243 ns) 5.732 ns pwm_fpga:pwm_control\|cnt_out_int\[5\] 4 REG LC_X5_Y4_N9 4 " "Info: 4: + IC(0.700 ns) + CELL(1.243 ns) = 5.732 ns; Loc. = LC_X5_Y4_N9; Fanout = 4; REG Node = 'pwm_fpga:pwm_control\|cnt_out_int\[5\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "1.943 ns" { pwm_fpga:pwm_control|cnt_out_int~3730 pwm_fpga:pwm_control|cnt_out_int[5] } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.643 ns 28.66 % " "Info: Total cell delay = 1.643 ns ( 28.66 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "4.089 ns 71.34 % " "Info: Total interconnect delay = 4.089 ns ( 71.34 % )" { } { } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "5.732 ns" { pwm_fpga:pwm_control|pwm pwm_fpga:pwm_control|process1~134 pwm_fpga:pwm_control|cnt_out_int~3730 pwm_fpga:pwm_control|cnt_out_int[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.732 ns" { pwm_fpga:pwm_control|pwm pwm_fpga:pwm_control|process1~134 pwm_fpga:pwm_control|cnt_out_int~3730 pwm_fpga:pwm_control|cnt_out_int[5] } { 0.000ns 0.924ns 2.465ns 0.700ns } { 0.000ns 0.200ns 0.200ns 1.243ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "-4.645 ns - Smallest " "Info: - Smallest clock skew is -4.645 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkfast destination 7.373 ns + Shortest register " "Info: + Shortest clock path from clock \"clkfast\" to destination register is 7.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkfast 1 CLK PIN_12 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { clkfast } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns pwm_clkdiv\[7\] 2 REG LC_X2_Y3_N7 18 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv\[7\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "2.561 ns" { clkfast pwm_clkdiv[7] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(0.918 ns) 7.373 ns pwm_fpga:pwm_control\|cnt_out_int\[5\] 3 REG LC_X5_Y4_N9 4 " "Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.373 ns; Loc. = LC_X5_Y4_N9; Fanout = 4; REG Node = 'pwm_fpga:pwm_control\|cnt_out_int\[5\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.649 ns" { pwm_clkdiv[7] pwm_fpga:pwm_control|cnt_out_int[5] } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 13 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 45.78 % " "Info: Total cell delay = 3.375 ns ( 45.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.998 ns 54.22 % " "Info: Total interconnect delay = 3.998 ns ( 54.22 % )" { } { } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "7.373 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|cnt_out_int[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.373 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|cnt_out_int[5] } { 0.000ns 0.000ns 1.267ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkfast source 12.018 ns - Longest register " "Info: - Longest clock path from clock \"clkfast\" to source register is 12.018 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkfast 1 CLK PIN_12 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { clkfast } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns pwm_clkdiv\[7\] 2 REG LC_X2_Y3_N7 18 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv\[7\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "2.561 ns" { clkfast pwm_clkdiv[7] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(1.294 ns) 7.749 ns pwm_fpga:pwm_control\|rco_int 3 REG LC_X5_Y3_N3 12 " "Info: 3: + IC(2.731 ns) + CELL(1.294 ns) = 7.749 ns; Loc. = LC_X5_Y3_N3; Fanout = 12; REG Node = 'pwm_fpga:pwm_control\|rco_int'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "4.025 ns" { pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.351 ns) + CELL(0.918 ns) 12.018 ns pwm_fpga:pwm_control\|pwm 4 REG LC_X7_Y4_N3 5 " "Info: 4: + IC(3.351 ns) + CELL(0.918 ns) = 12.018 ns; Loc. = LC_X7_Y4_N3; Fanout = 5; REG Node = 'pwm_fpga:pwm_control\|pwm'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "4.269 ns" { pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns 38.85 % " "Info: Total cell delay = 4.669 ns ( 38.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.349 ns 61.15 % " "Info: Total interconnect delay = 7.349 ns ( 61.15 % )" { } { } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "12.018 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.018 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } { 0.000ns 0.000ns 1.267ns 2.731ns 3.351ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "7.373 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|cnt_out_int[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.373 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|cnt_out_int[5] } { 0.000ns 0.000ns 1.267ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "12.018 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.018 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } { 0.000ns 0.000ns 1.267ns 2.731ns 3.351ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 13 -1 0 } } } 0} { "Info" "ITDB_INVERTED_CLOCK_FOUND" "" "Info: Delay path is controlled by inverted clocks -- if clock duty cycle is 50, fmax is divided by two" { } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 8 -1 0 } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 13 -1 0 } } } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "5.732 ns" { pwm_fpga:pwm_control|pwm pwm_fpga:pwm_control|process1~134 pwm_fpga:pwm_control|cnt_out_int~3730 pwm_fpga:pwm_control|cnt_out_int[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "5.732 ns" { pwm_fpga:pwm_control|pwm pwm_fpga:pwm_control|process1~134 pwm_fpga:pwm_control|cnt_out_int~3730 pwm_fpga:pwm_control|cnt_out_int[5] } { 0.000ns 0.924ns 2.465ns 0.700ns } { 0.000ns 0.200ns 0.200ns 1.243ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "7.373 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|cnt_out_int[5] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.373 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|cnt_out_int[5] } { 0.000ns 0.000ns 1.267ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "12.018 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.018 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } { 0.000ns 0.000ns 1.267ns 2.731ns 3.351ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } } 0}
{ "Info" "ITDB_TSU_RESULT" "pwm_fpga:pwm_control\|reg_out\[0\] SW\[0\] clkfast -3.318 ns register " "Info: tsu for register \"pwm_fpga:pwm_control\|reg_out\[0\]\" (data pin = \"SW\[0\]\", clock pin = \"clkfast\") is -3.318 ns" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.722 ns + Longest pin register " "Info: + Longest pin to register delay is 3.722 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.132 ns) 1.132 ns SW\[0\] 1 PIN PIN_28 2 " "Info: 1: + IC(0.000 ns) + CELL(1.132 ns) = 1.132 ns; Loc. = PIN_28; Fanout = 2; PIN Node = 'SW\[0\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { SW[0] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 10 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.310 ns) + CELL(0.280 ns) 3.722 ns pwm_fpga:pwm_control\|reg_out\[0\] 2 REG LC_X2_Y4_N6 1 " "Info: 2: + IC(2.310 ns) + CELL(0.280 ns) = 3.722 ns; Loc. = LC_X2_Y4_N6; Fanout = 1; REG Node = 'pwm_fpga:pwm_control\|reg_out\[0\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "2.590 ns" { SW[0] pwm_fpga:pwm_control|reg_out[0] } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.412 ns 37.94 % " "Info: Total cell delay = 1.412 ns ( 37.94 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "2.310 ns 62.06 % " "Info: Total interconnect delay = 2.310 ns ( 62.06 % )" { } { } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.722 ns" { SW[0] pwm_fpga:pwm_control|reg_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.722 ns" { SW[0] SW[0]~combout pwm_fpga:pwm_control|reg_out[0] } { 0.000ns 0.000ns 2.310ns } { 0.000ns 1.132ns 0.280ns } } } } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.333 ns + " "Info: + Micro setup delay of destination is 0.333 ns" { } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 12 -1 0 } } } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkfast destination 7.373 ns - Shortest register " "Info: - Shortest clock path from clock \"clkfast\" to destination register is 7.373 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkfast 1 CLK PIN_12 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { clkfast } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns pwm_clkdiv\[7\] 2 REG LC_X2_Y3_N7 18 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv\[7\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "2.561 ns" { clkfast pwm_clkdiv[7] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(0.918 ns) 7.373 ns pwm_fpga:pwm_control\|reg_out\[0\] 3 REG LC_X2_Y4_N6 1 " "Info: 3: + IC(2.731 ns) + CELL(0.918 ns) = 7.373 ns; Loc. = LC_X2_Y4_N6; Fanout = 1; REG Node = 'pwm_fpga:pwm_control\|reg_out\[0\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.649 ns" { pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[0] } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "3.375 ns 45.78 % " "Info: Total cell delay = 3.375 ns ( 45.78 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "3.998 ns 54.22 % " "Info: Total interconnect delay = 3.998 ns ( 54.22 % )" { } { } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "7.373 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.373 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[0] } { 0.000ns 0.000ns 1.267ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.722 ns" { SW[0] pwm_fpga:pwm_control|reg_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.722 ns" { SW[0] SW[0]~combout pwm_fpga:pwm_control|reg_out[0] } { 0.000ns 0.000ns 2.310ns } { 0.000ns 1.132ns 0.280ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "7.373 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[0] } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "7.373 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|reg_out[0] } { 0.000ns 0.000ns 1.267ns 2.731ns } { 0.000ns 1.163ns 1.294ns 0.918ns } } } } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "clkfast pwm_out pwm_fpga:pwm_control\|pwm 15.511 ns register " "Info: tco from clock \"clkfast\" to destination pin \"pwm_out\" through register \"pwm_fpga:pwm_control\|pwm\" is 15.511 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "clkfast source 12.018 ns + Longest register " "Info: + Longest clock path from clock \"clkfast\" to source register is 12.018 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.163 ns) 1.163 ns clkfast 1 CLK PIN_12 8 " "Info: 1: + IC(0.000 ns) + CELL(1.163 ns) = 1.163 ns; Loc. = PIN_12; Fanout = 8; CLK Node = 'clkfast'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { clkfast } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 11 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.267 ns) + CELL(1.294 ns) 3.724 ns pwm_clkdiv\[7\] 2 REG LC_X2_Y3_N7 18 " "Info: 2: + IC(1.267 ns) + CELL(1.294 ns) = 3.724 ns; Loc. = LC_X2_Y3_N7; Fanout = 18; REG Node = 'pwm_clkdiv\[7\]'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "2.561 ns" { clkfast pwm_clkdiv[7] } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 19 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(2.731 ns) + CELL(1.294 ns) 7.749 ns pwm_fpga:pwm_control\|rco_int 3 REG LC_X5_Y3_N3 12 " "Info: 3: + IC(2.731 ns) + CELL(1.294 ns) = 7.749 ns; Loc. = LC_X5_Y3_N3; Fanout = 12; REG Node = 'pwm_fpga:pwm_control\|rco_int'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "4.025 ns" { pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 14 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(3.351 ns) + CELL(0.918 ns) 12.018 ns pwm_fpga:pwm_control\|pwm 4 REG LC_X7_Y4_N3 5 " "Info: 4: + IC(3.351 ns) + CELL(0.918 ns) = 12.018 ns; Loc. = LC_X7_Y4_N3; Fanout = 5; REG Node = 'pwm_fpga:pwm_control\|pwm'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "4.269 ns" { pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 8 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "4.669 ns 38.85 % " "Info: Total cell delay = 4.669 ns ( 38.85 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "7.349 ns 61.15 % " "Info: Total interconnect delay = 7.349 ns ( 61.15 % )" { } { } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "12.018 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.018 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } { 0.000ns 0.000ns 1.267ns 2.731ns 3.351ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } } 0} { "Info" "ITDB_FULL_TCO_DELAY" "0.376 ns + " "Info: + Micro clock to output delay of source is 0.376 ns" { } { { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 8 -1 0 } } } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.117 ns + Longest register pin " "Info: + Longest register to pin delay is 3.117 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns pwm_fpga:pwm_control\|pwm 1 REG LC_X7_Y4_N3 5 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC_X7_Y4_N3; Fanout = 5; REG Node = 'pwm_fpga:pwm_control\|pwm'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "" { pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "pwm_fpga.vhdl" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl" 8 -1 0 } } } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.795 ns) + CELL(2.322 ns) 3.117 ns pwm_out 2 PIN PIN_73 0 " "Info: 2: + IC(0.795 ns) + CELL(2.322 ns) = 3.117 ns; Loc. = PIN_73; Fanout = 0; PIN Node = 'pwm_out'" { } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.117 ns" { pwm_fpga:pwm_control|pwm pwm_out } "NODE_NAME" } "" } } { "pwmtest.v" "" { Text "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v" 12 -1 0 } } } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.322 ns 74.49 % " "Info: Total cell delay = 2.322 ns ( 74.49 % )" { } { } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "0.795 ns 25.51 % " "Info: Total interconnect delay = 0.795 ns ( 25.51 % )" { } { } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.117 ns" { pwm_fpga:pwm_control|pwm pwm_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.117 ns" { pwm_fpga:pwm_control|pwm pwm_out } { 0.000ns 0.795ns } { 0.000ns 2.322ns } } } } 0} } { { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "12.018 ns" { clkfast pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "12.018 ns" { clkfast clkfast~combout pwm_clkdiv[7] pwm_fpga:pwm_control|rco_int pwm_fpga:pwm_control|pwm } { 0.000ns 0.000ns 1.267ns 2.731ns 3.351ns } { 0.000ns 1.163ns 1.294ns 1.294ns 0.918ns } } } { "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" "" { Report "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest_cmp.qrpt" Compiler "pwmtest" "UNKNOWN" "V1" "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/db/pwmtest.quartus_db" { Floorplan "H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/" "" "3.117 ns" { pwm_fpga:pwm_control|pwm pwm_out } "NODE_NAME" } "" } } { "d:/altera/quartus50/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus50/bin/Technology_Viewer.qrui" "3.117 ns" { pwm_fpga:pwm_control|pwm pwm_out } { 0.000ns 0.795ns } { 0.000ns 2.322ns } } } } 0}
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