pwmtest.hier_info

利用VHDL实现CPLD（EMP240T100C5）的PWM输出

|pwmtest
SW[0] => SW[0]~7.IN1
SW[1] => SW[1]~6.IN1
SW[2] => SW[2]~5.IN1
SW[3] => SW[3]~4.IN1
SW[4] => SW[4]~3.IN1
SW[5] => SW[5]~2.IN1
SW[6] => SW[6]~1.IN1
SW[7] => SW[7]~0.IN1
clkfast => pwm_clkdiv[6].CLK
clkfast => pwm_clkdiv[5].CLK
clkfast => pwm_clkdiv[4].CLK
clkfast => pwm_clkdiv[3].CLK
clkfast => pwm_clkdiv[2].CLK
clkfast => pwm_clkdiv[1].CLK
clkfast => pwm_clkdiv[0].CLK
clkfast => pwm_clkdiv[7].CLK
pwm_out <= pwm_fpga:pwm_control.pwm
LED[0] <= SW[0]~7.DB_MAX_OUTPUT_PORT_TYPE
LED[1] <= SW[1]~6.DB_MAX_OUTPUT_PORT_TYPE
LED[2] <= SW[2]~5.DB_MAX_OUTPUT_PORT_TYPE
LED[3] <= SW[3]~4.DB_MAX_OUTPUT_PORT_TYPE
LED[4] <= SW[4]~3.DB_MAX_OUTPUT_PORT_TYPE
LED[5] <= SW[5]~2.DB_MAX_OUTPUT_PORT_TYPE
LED[6] <= SW[6]~1.DB_MAX_OUTPUT_PORT_TYPE
LED[7] <= SW[7]~0.DB_MAX_OUTPUT_PORT_TYPE
RST => RST~0.IN1


|pwmtest|pwm_fpga:pwm_control
clock => reg_out[6].CLK
clock => reg_out[5].CLK
clock => reg_out[4].CLK
clock => reg_out[3].CLK
clock => reg_out[2].CLK
clock => reg_out[1].CLK
clock => reg_out[0].CLK
clock => cnt_out_int[7].CLK
clock => cnt_out_int[6].CLK
clock => cnt_out_int[5].CLK
clock => cnt_out_int[4].CLK
clock => cnt_out_int[3].CLK
clock => cnt_out_int[2].CLK
clock => cnt_out_int[1].CLK
clock => cnt_out_int[0].CLK
clock => rco_int.CLK
clock => reg_out[7].CLK
reset => reg_out[6].ACLR
reset => reg_out[5].ACLR
reset => reg_out[4].ACLR
reset => reg_out[3].ACLR
reset => reg_out[2].ACLR
reset => reg_out[1].ACLR
reset => reg_out[0].ACLR
reset => rco_int.PRESET
reset => pwm_int.ACLR
reset => reg_out[7].ACLR
Data_value[0] => reg_out[0].DATAIN
Data_value[1] => reg_out[1].DATAIN
Data_value[2] => reg_out[2].DATAIN
Data_value[3] => reg_out[3].DATAIN
Data_value[4] => reg_out[4].DATAIN
Data_value[5] => reg_out[5].DATAIN
Data_value[6] => reg_out[6].DATAIN
Data_value[7] => reg_out[7].DATAIN
pwm <= pwm_int.DB_MAX_OUTPUT_PORT_TYPE