pwmtest.map.eqn

利用VHDL实现CPLD（EMP240T100C5）的PWM输出

-- Copyright (C) 1991-2005 Altera Corporation
-- Your use of Altera Corporation's design tools, logic functions 
-- and other software and tools, and its AMPP partner logic 
-- functions, and any output files any of the foregoing 
-- (including device programming or simulation files), and any 
-- associated documentation or information are expressly subject 
-- to the terms and conditions of the Altera Program License 
-- Subscription Agreement, Altera MegaCore Function License 
-- Agreement, or other applicable license agreement, including, 
-- without limitation, that your use is for the sole purpose of 
-- programming logic devices manufactured by Altera and sold by 
-- Altera or its authorized distributors.  Please refer to the 
-- applicable agreement for further details.
--B1_pwm is pwm_fpga:pwm_control|pwm
--operation mode is normal

B1_pwm_lut_out = !B1_pwm;
B1_pwm = DFFEAS(B1_pwm_lut_out, !B1_rco_int, !RST, , , , , , );


--B1_rco_int is pwm_fpga:pwm_control|rco_int
--operation mode is normal

B1_rco_int_lut_out = B1_cnt_out_int[7] & !B1L4 # !B1_cnt_out_int[7] & (!B1L5);
B1_rco_int = DFFEAS(B1_rco_int_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--B1_cnt_out_int[6] is pwm_fpga:pwm_control|cnt_out_int[6]
--operation mode is normal

B1_cnt_out_int[6]_lut_out = B1_cnt_out_int[6] $ (B1L61 & (B1L71));
B1_cnt_out_int[6] = DFFEAS(B1_cnt_out_int[6]_lut_out, pwm_clkdiv[7], VCC, , , B1_reg_out[6], !B1_rco_int, , );


--B1_cnt_out_int[5] is pwm_fpga:pwm_control|cnt_out_int[5]
--operation mode is normal

B1_cnt_out_int[5]_lut_out = !B1L81;
B1_cnt_out_int[5] = DFFEAS(B1_cnt_out_int[5]_lut_out, pwm_clkdiv[7], VCC, , B1L91, B1_reg_out[5], !B1_rco_int, , );


--B1_cnt_out_int[4] is pwm_fpga:pwm_control|cnt_out_int[4]
--operation mode is normal

B1_cnt_out_int[4]_lut_out = !B1L02;
B1_cnt_out_int[4] = DFFEAS(B1_cnt_out_int[4]_lut_out, pwm_clkdiv[7], VCC, , B1L12, B1_reg_out[4], !B1_rco_int, , );


--B1_cnt_out_int[3] is pwm_fpga:pwm_control|cnt_out_int[3]
--operation mode is normal

B1_cnt_out_int[3]_lut_out = B1L22;
B1_cnt_out_int[3] = DFFEAS(B1_cnt_out_int[3]_lut_out, pwm_clkdiv[7], VCC, , , B1_reg_out[3], !B1_rco_int, , );


--B1_cnt_out_int[2] is pwm_fpga:pwm_control|cnt_out_int[2]
--operation mode is normal

B1_cnt_out_int[2]_lut_out = B1L32;
B1_cnt_out_int[2] = DFFEAS(B1_cnt_out_int[2]_lut_out, pwm_clkdiv[7], VCC, , , B1_reg_out[2], !B1_rco_int, , );


--B1_cnt_out_int[1] is pwm_fpga:pwm_control|cnt_out_int[1]
--operation mode is normal

B1_cnt_out_int[1]_lut_out = B1L52;
B1_cnt_out_int[1] = DFFEAS(B1_cnt_out_int[1]_lut_out, pwm_clkdiv[7], VCC, , , B1_reg_out[1], !B1_rco_int, , );


--B1_cnt_out_int[0] is pwm_fpga:pwm_control|cnt_out_int[0]
--operation mode is normal

B1_cnt_out_int[0]_lut_out = !B1_cnt_out_int[0];
B1_cnt_out_int[0] = DFFEAS(B1_cnt_out_int[0]_lut_out, pwm_clkdiv[7], VCC, , B1L62, B1_reg_out[0], !B1_rco_int, , );


--B1L3 is pwm_fpga:pwm_control|cnt_out_int[0]~3721
--operation mode is normal

B1L3 = B1_cnt_out_int[3] & B1_cnt_out_int[2] & B1_cnt_out_int[1] & B1_cnt_out_int[0];


--B1L4 is pwm_fpga:pwm_control|cnt_out_int[0]~3722
--operation mode is normal

B1L4 = B1_cnt_out_int[6] & B1_cnt_out_int[5] & B1_cnt_out_int[4] & B1L3;


--B1L51 is pwm_fpga:pwm_control|cnt_out_int~3723
--operation mode is normal

B1L51 = !B1_cnt_out_int[3] & !B1_cnt_out_int[2] & !B1_cnt_out_int[1] & !B1_cnt_out_int[0];


--B1L5 is pwm_fpga:pwm_control|cnt_out_int[0]~3724
--operation mode is normal

B1L5 = B1L51 & !B1_cnt_out_int[6] & !B1_cnt_out_int[5] & !B1_cnt_out_int[4];


--B1_cnt_out_int[7] is pwm_fpga:pwm_control|cnt_out_int[7]
--operation mode is normal

B1_cnt_out_int[7]_lut_out = B1L82;
B1_cnt_out_int[7] = DFFEAS(B1_cnt_out_int[7]_lut_out, pwm_clkdiv[7], VCC, , , B1_reg_out[7], !B1_rco_int, , );


--pwm_clkdiv[7] is pwm_clkdiv[7]
--operation mode is normal

pwm_clkdiv[7]_carry_eqn = A1L53;
pwm_clkdiv[7]_lut_out = pwm_clkdiv[7] $ (pwm_clkdiv[7]_carry_eqn);
pwm_clkdiv[7] = DFFEAS(pwm_clkdiv[7]_lut_out, clkfast, VCC, , , , , , );


--B1L6 is pwm_fpga:pwm_control|cnt_out_int[0]~3725
--operation mode is normal

B1L6 = B1_cnt_out_int[2] & B1_cnt_out_int[1] & B1_cnt_out_int[0];


--B1L61 is pwm_fpga:pwm_control|cnt_out_int~3726
--operation mode is normal

B1L61 = B1_cnt_out_int[4] & (B1_cnt_out_int[3] & B1L6) # !B1_cnt_out_int[4] & B1L51;


--B1L33 is pwm_fpga:pwm_control|process1~133
--operation mode is normal

B1L33 = B1_rco_int & !B1_pwm & (B1_cnt_out_int[7] # !B1L5);


--B1L43 is pwm_fpga:pwm_control|process1~134
--operation mode is normal

B1L43 = B1_pwm & B1_rco_int & (!B1L4 # !B1_cnt_out_int[7]);


--B1L71 is pwm_fpga:pwm_control|cnt_out_int~3727
--operation mode is normal

B1L71 = B1_cnt_out_int[5] & (B1L43 & B1_cnt_out_int[4]) # !B1_cnt_out_int[5] & B1L33 & !B1L43 & !B1_cnt_out_int[4];


--B1_reg_out[6] is pwm_fpga:pwm_control|reg_out[6]
--operation mode is normal

B1_reg_out[6]_lut_out = SW[6];
B1_reg_out[6] = DFFEAS(B1_reg_out[6]_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--B1L81 is pwm_fpga:pwm_control|cnt_out_int~3729
--operation mode is normal

B1L81 = B1_cnt_out_int[5] $ (B1L43 & !B1L3 # !B1L43 & (!B1L51));


--B1L91 is pwm_fpga:pwm_control|cnt_out_int~3730
--operation mode is normal

B1L91 = B1_cnt_out_int[4] & B1L43 # !B1_cnt_out_int[4] & !B1L43 & B1L33;


--B1_reg_out[5] is pwm_fpga:pwm_control|reg_out[5]
--operation mode is normal

B1_reg_out[5]_lut_out = SW[5];
B1_reg_out[5] = DFFEAS(B1_reg_out[5]_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--B1L7 is pwm_fpga:pwm_control|cnt_out_int[0]~3731
--operation mode is normal

B1L7 = !B1_cnt_out_int[2] & !B1_cnt_out_int[1] & !B1_cnt_out_int[0];


--B1L02 is pwm_fpga:pwm_control|cnt_out_int~3732
--operation mode is normal

B1L02 = B1_cnt_out_int[4] $ (B1L43 & !B1L6 # !B1L43 & (!B1L7));


--B1L12 is pwm_fpga:pwm_control|cnt_out_int~3733
--operation mode is normal

B1L12 = B1_cnt_out_int[3] & B1L43 # !B1_cnt_out_int[3] & !B1L43 & B1L33;


--B1_reg_out[4] is pwm_fpga:pwm_control|reg_out[4]
--operation mode is normal

B1_reg_out[4]_lut_out = SW[4];
B1_reg_out[4] = DFFEAS(B1_reg_out[4]_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--B1L22 is pwm_fpga:pwm_control|cnt_out_int~3734
--operation mode is normal

B1L22 = B1_cnt_out_int[3] $ (B1L43 & B1L6 # !B1L43 & (B1L92));


--B1_reg_out[3] is pwm_fpga:pwm_control|reg_out[3]
--operation mode is normal

B1_reg_out[3]_lut_out = SW[3];
B1_reg_out[3] = DFFEAS(B1_reg_out[3]_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--B1L13 is pwm_fpga:pwm_control|INC~206
--operation mode is normal

B1L13 = B1_cnt_out_int[2] $ (!B1_cnt_out_int[0] # !B1_cnt_out_int[1]);


--B1L32 is pwm_fpga:pwm_control|cnt_out_int~3735
--operation mode is normal

B1L32 = B1L43 & (!B1L3 & !B1L13) # !B1L43 & B1L03;


--B1_reg_out[2] is pwm_fpga:pwm_control|reg_out[2]
--operation mode is normal

B1_reg_out[2]_lut_out = SW[2];
B1_reg_out[2] = DFFEAS(B1_reg_out[2]_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--B1L42 is pwm_fpga:pwm_control|cnt_out_int~3736
--operation mode is normal

B1L42 = B1L33 & (B1L51 # B1_cnt_out_int[1] $ !B1_cnt_out_int[0]) # !B1L33 & B1_cnt_out_int[1];


--B1L23 is pwm_fpga:pwm_control|INC~207
--operation mode is normal

B1L23 = B1_cnt_out_int[1] $ B1_cnt_out_int[0];


--B1L52 is pwm_fpga:pwm_control|cnt_out_int~3737
--operation mode is normal

B1L52 = B1L43 & (B1L23 & !B1L3) # !B1L43 & B1L42;


--B1_reg_out[1] is pwm_fpga:pwm_control|reg_out[1]
--operation mode is normal

B1_reg_out[1]_lut_out = SW[1];
B1_reg_out[1] = DFFEAS(B1_reg_out[1]_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--B1L62 is pwm_fpga:pwm_control|cnt_out_int~3738
--operation mode is normal

B1L62 = B1L43 # B1L33;


--B1_reg_out[0] is pwm_fpga:pwm_control|reg_out[0]
--operation mode is normal

B1_reg_out[0]_lut_out = SW[0];
B1_reg_out[0] = DFFEAS(B1_reg_out[0]_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--B1L72 is pwm_fpga:pwm_control|cnt_out_int~3739
--operation mode is normal

B1L72 = B1_cnt_out_int[7] & (B1_pwm # !B1L5 # !B1_rco_int);


--B1L82 is pwm_fpga:pwm_control|cnt_out_int~3740
--operation mode is normal

B1L82 = B1L43 & (B1_cnt_out_int[7] $ B1L4) # !B1L43 & B1L72;


--B1_reg_out[7] is pwm_fpga:pwm_control|reg_out[7]
--operation mode is normal

B1_reg_out[7]_lut_out = SW[7];
B1_reg_out[7] = DFFEAS(B1_reg_out[7]_lut_out, pwm_clkdiv[7], !RST, , , , , , );


--pwm_clkdiv[6] is pwm_clkdiv[6]
--operation mode is arithmetic

pwm_clkdiv[6]_carry_eqn = A1L33;
pwm_clkdiv[6]_lut_out = pwm_clkdiv[6] $ (!pwm_clkdiv[6]_carry_eqn);
pwm_clkdiv[6] = DFFEAS(pwm_clkdiv[6]_lut_out, clkfast, VCC, , , , , , );

--A1L53 is pwm_clkdiv[6]~62
--operation mode is arithmetic

A1L53 = CARRY(pwm_clkdiv[6] & (!A1L33));


--pwm_clkdiv[5] is pwm_clkdiv[5]
--operation mode is arithmetic

pwm_clkdiv[5]_carry_eqn = A1L13;
pwm_clkdiv[5]_lut_out = pwm_clkdiv[5] $ (pwm_clkdiv[5]_carry_eqn);
pwm_clkdiv[5] = DFFEAS(pwm_clkdiv[5]_lut_out, clkfast, VCC, , , , , , );

--A1L33 is pwm_clkdiv[5]~66
--operation mode is arithmetic

A1L33 = CARRY(!A1L13 # !pwm_clkdiv[5]);


--pwm_clkdiv[4] is pwm_clkdiv[4]
--operation mode is arithmetic

pwm_clkdiv[4]_carry_eqn = A1L92;
pwm_clkdiv[4]_lut_out = pwm_clkdiv[4] $ (!pwm_clkdiv[4]_carry_eqn);
pwm_clkdiv[4] = DFFEAS(pwm_clkdiv[4]_lut_out, clkfast, VCC, , , , , , );

--A1L13 is pwm_clkdiv[4]~70
--operation mode is arithmetic

A1L13 = CARRY(pwm_clkdiv[4] & (!A1L92));


--pwm_clkdiv[3] is pwm_clkdiv[3]
--operation mode is arithmetic

pwm_clkdiv[3]_carry_eqn = A1L72;
pwm_clkdiv[3]_lut_out = pwm_clkdiv[3] $ (pwm_clkdiv[3]_carry_eqn);
pwm_clkdiv[3] = DFFEAS(pwm_clkdiv[3]_lut_out, clkfast, VCC, , , , , , );

--A1L92 is pwm_clkdiv[3]~74
--operation mode is arithmetic

A1L92 = CARRY(!A1L72 # !pwm_clkdiv[3]);


--pwm_clkdiv[2] is pwm_clkdiv[2]
--operation mode is arithmetic

pwm_clkdiv[2]_carry_eqn = A1L52;
pwm_clkdiv[2]_lut_out = pwm_clkdiv[2] $ (!pwm_clkdiv[2]_carry_eqn);
pwm_clkdiv[2] = DFFEAS(pwm_clkdiv[2]_lut_out, clkfast, VCC, , , , , , );

--A1L72 is pwm_clkdiv[2]~78
--operation mode is arithmetic

A1L72 = CARRY(pwm_clkdiv[2] & (!A1L52));


--pwm_clkdiv[1] is pwm_clkdiv[1]
--operation mode is arithmetic

pwm_clkdiv[1]_carry_eqn = A1L32;
pwm_clkdiv[1]_lut_out = pwm_clkdiv[1] $ (pwm_clkdiv[1]_carry_eqn);
pwm_clkdiv[1] = DFFEAS(pwm_clkdiv[1]_lut_out, clkfast, VCC, , , , , , );

--A1L52 is pwm_clkdiv[1]~82
--operation mode is arithmetic

A1L52 = CARRY(!A1L32 # !pwm_clkdiv[1]);


--pwm_clkdiv[0] is pwm_clkdiv[0]
--operation mode is arithmetic

pwm_clkdiv[0]_lut_out = !pwm_clkdiv[0];
pwm_clkdiv[0] = DFFEAS(pwm_clkdiv[0]_lut_out, clkfast, VCC, , , , , , );

--A1L32 is pwm_clkdiv[0]~86
--operation mode is arithmetic

A1L32 = CARRY(pwm_clkdiv[0]);


--B1L92 is pwm_fpga:pwm_control|cnt_out_int~3741
--operation mode is normal

B1L92 = !B1_cnt_out_int[1] & !B1_cnt_out_int[0] & !B1_cnt_out_int[2] & B1L33;


--B1L03 is pwm_fpga:pwm_control|cnt_out_int~3742
--operation mode is normal

B1L03 = B1_cnt_out_int[2] $ (!B1_cnt_out_int[1] & !B1_cnt_out_int[0] & B1L33);


--SW[0] is SW[0]
--operation mode is input

SW[0] = INPUT();


--SW[1] is SW[1]
--operation mode is input

SW[1] = INPUT();


--SW[2] is SW[2]
--operation mode is input

SW[2] = INPUT();


--SW[3] is SW[3]
--operation mode is input

SW[3] = INPUT();


--SW[4] is SW[4]
--operation mode is input

SW[4] = INPUT();


--SW[5] is SW[5]
--operation mode is input

SW[5] = INPUT();


--SW[6] is SW[6]
--operation mode is input

SW[6] = INPUT();


--SW[7] is SW[7]
--operation mode is input

SW[7] = INPUT();


--RST is RST
--operation mode is input

RST = INPUT();


--clkfast is clkfast
--operation mode is input

clkfast = INPUT();


--pwm_out is pwm_out
--operation mode is output

pwm_out = OUTPUT(B1_pwm);


--LED[0] is LED[0]
--operation mode is output

LED[0] = OUTPUT(!SW[0]);


--LED[1] is LED[1]
--operation mode is output

LED[1] = OUTPUT(!SW[1]);


--LED[2] is LED[2]
--operation mode is output

LED[2] = OUTPUT(!SW[2]);


--LED[3] is LED[3]
--operation mode is output

LED[3] = OUTPUT(!SW[3]);


--LED[4] is LED[4]
--operation mode is output

LED[4] = OUTPUT(!SW[4]);


--LED[5] is LED[5]
--operation mode is output

LED[5] = OUTPUT(!SW[5]);


--LED[6] is LED[6]
--operation mode is output

LED[6] = OUTPUT(!SW[6]);


--LED[7] is LED[7]
--operation mode is output

LED[7] = OUTPUT(!SW[7]);