📄 pwmtest.map.rpt
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Analysis & Synthesis report for pwmtest
Thu May 31 18:54:36 2007
Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
---------------------
; Table of Contents ;
---------------------
1. Legal Notice
2. Analysis & Synthesis Summary
3. Analysis & Synthesis Settings
4. Analysis & Synthesis Source Files Read
5. Analysis & Synthesis Resource Usage Summary
6. Analysis & Synthesis Resource Utilization by Entity
7. General Register Statistics
8. Inverted Register Statistics
9. Analysis & Synthesis Equations
10. Analysis & Synthesis Messages
----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions
and other software and tools, and its AMPP partner logic
functions, and any output files any of the foregoing
(including device programming or simulation files), and any
associated documentation or information are expressly subject
to the terms and conditions of the Altera Program License
Subscription Agreement, Altera MegaCore Function License
Agreement, or other applicable license agreement, including,
without limitation, that your use is for the sole purpose of
programming logic devices manufactured by Altera and sold by
Altera or its authorized distributors. Please refer to the
applicable agreement for further details.
+-----------------------------------------------------------------------------+
; Analysis & Synthesis Summary ;
+-----------------------------+-----------------------------------------------+
; Analysis & Synthesis Status ; Successful - Thu May 31 18:54:36 2007 ;
; Quartus II Version ; 5.0 Build 168 06/22/2005 SP 1 SJ Full Version ;
; Revision Name ; pwmtest ;
; Top-level Entity Name ; pwmtest ;
; Family ; MAX II ;
; Total logic elements ; 51 ;
; Total pins ; 19 ;
; Total virtual pins ; 0 ;
; UFM blocks ; 0 ;
+-----------------------------+-----------------------------------------------+
+---------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Settings ;
+--------------------------------------------------------------------+--------------+---------------+
; Option ; Setting ; Default Value ;
+--------------------------------------------------------------------+--------------+---------------+
; Device ; EPM240T100C5 ; ;
; Top-level entity name ; pwmtest ; pwmtest ;
; Family name ; MAX II ; Stratix ;
; Use smart compilation ; Off ; Off ;
; Restructure Multiplexers ; Auto ; Auto ;
; Create Debugging Nodes for IP Cores ; off ; off ;
; Preserve fewer node names ; On ; On ;
; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
; VHDL Version ; VHDL93 ; VHDL93 ;
; State Machine Processing ; Auto ; Auto ;
; Extract Verilog State Machines ; On ; On ;
; Extract VHDL State Machines ; On ; On ;
; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
; NOT Gate Push-Back ; On ; On ;
; Power-Up Don't Care ; On ; On ;
; Remove Redundant Logic Cells ; Off ; Off ;
; Remove Duplicate Registers ; On ; On ;
; Ignore CARRY Buffers ; Off ; Off ;
; Ignore CASCADE Buffers ; Off ; Off ;
; Ignore GLOBAL Buffers ; Off ; Off ;
; Ignore ROW GLOBAL Buffers ; Off ; Off ;
; Ignore LCELL Buffers ; Off ; Off ;
; Ignore SOFT Buffers ; On ; On ;
; Limit AHDL Integers to 32 Bits ; Off ; Off ;
; Optimization Technique -- MAX II ; Balanced ; Balanced ;
; Carry Chain Length -- Stratix/Stratix GX/Cyclone/MAX II/Cyclone II ; 70 ; 70 ;
; Auto Carry Chains ; On ; On ;
; Auto Open-Drain Pins ; On ; On ;
; Remove Duplicate Logic ; On ; On ;
; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
; Perform gate-level register retiming ; Off ; Off ;
; Allow register retiming to trade off Tsu/Tco with Fmax ; On ; On ;
; Auto Shift Register Replacement ; On ; On ;
; Auto Clock Enable Replacement ; On ; On ;
; Allows Synchronous Control Signal Usage in Normal Mode Logic Cells ; On ; On ;
; Auto RAM Block Balancing ; On ; On ;
; Auto Resource Sharing ; Off ; Off ;
; Maximum Number of M512 Memory Blocks ; -1 ; -1 ;
; Maximum Number of M4K Memory Blocks ; -1 ; -1 ;
; Maximum Number of M-RAM Memory Blocks ; -1 ; -1 ;
; Ignore translate_off and translate_on Synthesis Directives ; Off ; Off ;
; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
+--------------------------------------------------------------------+--------------+---------------+
+----------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+
; pwm_fpga.vhdl ; yes ; User VHDL File ; H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwm_fpga.vhdl ;
; pwmtest.v ; yes ; User Verilog HDL File ; H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.v ;
+----------------------------------+-----------------+------------------------+----------------------------------------------------------------+
+---------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary ;
+-----------------------------------+---------------+
; Resource ; Usage ;
+-----------------------------------+---------------+
; Total logic elements ; 51 ;
; Total combinational functions ; 35 ;
; -- Total 4-input functions ; 18 ;
; -- Total 3-input functions ; 7 ;
; -- Total 2-input functions ; 2 ;
; -- Total 1-input functions ; 8 ;
; -- Total 0-input functions ; 0 ;
; Combinational cells for routing ; 0 ;
; Total registers ; 26 ;
; Total logic cells in carry chains ; 8 ;
; I/O pins ; 19 ;
; Maximum fan-out node ; pwm_clkdiv[7] ;
; Maximum fan-out ; 18 ;
; Total fan-out ; 192 ;
; Average fan-out ; 2.74 ;
+-----------------------------------+---------------+
+----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------+
; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; UFM Blocks ; Pins ; Virtual Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Full Hierarchy Name ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------+
; |pwmtest ; 51 (8) ; 26 ; 0 ; 19 ; 0 ; 25 (0) ; 16 (0) ; 10 (8) ; 8 (8) ; |pwmtest ;
; |pwm_fpga:pwm_control| ; 43 (43) ; 18 ; 0 ; 0 ; 0 ; 25 (25) ; 16 (16) ; 2 (2) ; 0 (0) ; |pwmtest|pwm_fpga:pwm_control ;
+----------------------------+-------------+--------------+------------+------+--------------+--------------+-------------------+------------------+-----------------+-------------------------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
+------------------------------------------------------+
; General Register Statistics ;
+----------------------------------------------+-------+
; Statistic ; Value ;
+----------------------------------------------+-------+
; Total registers ; 26 ;
; Number of registers using Synchronous Clear ; 0 ;
; Number of registers using Synchronous Load ; 0 ;
; Number of registers using Asynchronous Clear ; 10 ;
; Number of registers using Asynchronous Load ; 8 ;
; Number of registers using Clock Enable ; 3 ;
; Number of registers using Preset ; 0 ;
+----------------------------------------------+-------+
+--------------------------------------------------+
; Inverted Register Statistics ;
+----------------------------------------+---------+
; Inverted Register ; Fan out ;
+----------------------------------------+---------+
; pwm_fpga:pwm_control|rco_int ; 12 ;
; Total number of inverted registers = 1 ; ;
+----------------------------------------+---------+
+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in H:/work/docs/dboard/epm240/ver1/firmware/PWMtest/pwmtest.map.eqn.
+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
Info: Version 5.0 Build 168 06/22/2005 Service Pack 1 SJ Full Version
Info: Processing started: Thu May 31 18:54:32 2007
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off pwmtest -c pwmtest
Info: Found 2 design units, including 1 entities, in source file pwm_fpga.vhdl
Info: Found design unit 1: pwm_fpga-arch_pwm
Info: Found entity 1: pwm_fpga
Info: Found 1 design units, including 1 entities, in source file pwmtest.v
Info: Found entity 1: pwmtest
Info: Elaborating entity "pwmtest" for the top level hierarchy
Warning: Verilog HDL assignment warning at pwmtest.v(24): truncated value with size 32 to match size of target (8)
Info: Elaborating entity "pwm_fpga" for hierarchy "pwm_fpga:pwm_control"
Warning: VHDL Process Statement warning at pwm_fpga.vhdl(77): signal "pwm_int" is read inside the Process Statement but isn't in the Process Statement's sensivitity list
Info: Registers with preset signals will power-up high
Info: Implemented 70 device resources after synthesis - the final resource count might be different
Info: Implemented 10 input pins
Info: Implemented 9 output pins
Info: Implemented 51 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 2 warnings
Info: Processing ended: Thu May 31 18:54:36 2007
Info: Elapsed time: 00:00:04
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