pwmtest.tan.summary

利用VHDL实现CPLD（EMP240T100C5）的PWM输出

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -3.318 ns
From           : SW[0]
To             : pwm_fpga:pwm_control|reg_out[0]
From Clock     : 
To Clock       : clkfast
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 15.511 ns
From           : pwm_fpga:pwm_control|pwm
To             : pwm_out
From Clock     : clkfast
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 6.271 ns
From           : SW[7]
To             : LED[7]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 4.016 ns
From           : SW[4]
To             : pwm_fpga:pwm_control|reg_out[4]
From Clock     : 
To Clock       : clkfast
Failed Paths   : 0

Type           : Clock Setup: 'clkfast'
Slack          : N/A
Required Time  : None
Actual Time    : 45.10 MHz ( period = 22.172 ns )
From           : pwm_fpga:pwm_control|pwm
To             : pwm_fpga:pwm_control|cnt_out_int[5]
From Clock     : clkfast
To Clock       : clkfast
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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