traffic.v.bak

使用ALTERA上DE2平台

module Traffic
(
clc,
rst,
LEDR,
LEDG,
HEX0
);

input clc;
input rst;
output LEDR;
output LEDG;
output reg [6:0] HEX0;

reg [1:0] LEDR;
reg [1:0] LEDG;
reg [25:0] count;
reg [4:0] period;

initial
begin
	LEDR[0] = 1'b0;
	LEDR[1] = 1'b1;
	LEDG[0] = 1'b1;
	LEDG[1] = 1'b0;
	count[25:0] = 26'b0;
	period[3:0] =4'b0;
end

always @ (posedge count[25] or posedge rst)
begin
    if (rst)
		period[3:0] = 4'b0;
	else
		period[3:0] = period[3:0] + 4'b1;
end

always @ (posedge clc)
begin
	count[25:0] = count[25:0]+26'b1;
	// LED CTRL
	case (period[3:2])
	2'b00:	
	begin
		LEDR[0]=1'b0;
		LEDR[1]=1'b1;
		LEDG[0]=1'b1;
		LEDG[1]=1'b0;
	end
	2'b01:
	begin
		LEDR[0]=1'b0;
		LEDR[1]=1'b1;
		LEDG[0]=count[25];
		LEDG[1]=1'b0;
	end
	2'b10:
	begin
		LEDR[0]=1'b1;
		LEDR[1]=1'b0;
		LEDG[0]=1'b0;
		LEDG[1]=1'b1;
	end
	2'b11:	
	begin
		LEDR[0]=1'b1;
		LEDR[1]=1'b0;
		LEDG[0]=1'b0;
		LEDG[1]=count[25];
	end
	endcase
	// HEX ctrl
	case(period[3:0])
		4'h0:	HEX0 = 7'b 1000000;
		4'h1:	HEX0 = 7'b 1111001;
		4'h2:	HEX0 = 7'b 0100100;
		4'h3:	HEX0 = 7'b 0110000;
		4'h4:	HEX0 = 7'b 0011001;
		4'h5:	HEX0 = 7'b 0010010;
		4'h6:	HEX0 = 7'b 0000010;
		4'h7:	HEX0 = 7'b 1111000;
		
		4'h8:	HEX0 = 7'b 1000000;
		4'h9:	HEX0 = 7'b 1111001;
		4'ha:	HEX0 = 7'b 0100100;
		4'hb:	HEX0 = 7'b 0110000;
		4'hc:	HEX0 = 7'b 0011001;
		4'hd:	HEX0 = 7'b 0010010;
		4'he:	HEX0 = 7'b 0000010;
		4'hf:	HEX0 = 7'b 1111000;
	endcase
end
endmodule