traffic.tan.rpt

使用ALTERA上DE2平台

; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[1]  ; count[12]    ; clc        ; clc      ; None                        ; None                      ; 1.992 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[13] ; count[24]    ; clc        ; clc      ; None                        ; None                      ; 1.985 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[8]  ; count[19]    ; clc        ; clc      ; None                        ; None                      ; 1.979 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[6]  ; count[17]    ; clc        ; clc      ; None                        ; None                      ; 1.978 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[0]  ; count[11]    ; clc        ; clc      ; None                        ; None                      ; 1.961 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[2]  ; count[12]    ; clc        ; clc      ; None                        ; None                      ; 1.961 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[5]  ; count[15]    ; clc        ; clc      ; None                        ; None                      ; 1.947 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[7]  ; count[17]    ; clc        ; clc      ; None                        ; None                      ; 1.947 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[9]  ; count[19]    ; clc        ; clc      ; None                        ; None                      ; 1.947 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[12] ; count[21]    ; clc        ; clc      ; None                        ; None                      ; 1.946 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[4]  ; count[13]    ; clc        ; clc      ; None                        ; None                      ; 1.929 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[14] ; count[24]    ; clc        ; clc      ; None                        ; None                      ; 1.924 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[1]  ; count[11]    ; clc        ; clc      ; None                        ; None                      ; 1.921 ns                ;
; N/A                                     ; Restricted to 420.17 MHz ( period = 2.380 ns )      ; count[13] ; count[23]    ; clc        ; clc      ; None                        ; None                      ; 1.914 ns                ;
; Timing analysis restricted to 200 rows. ; To change the limit use Settings (Assignments menu) ;           ;              ;            ;          ;                             ;                           ;                         ;
+-----------------------------------------+-----------------------------------------------------+-----------+--------------+------------+----------+-----------------------------+---------------------------+-------------------------+


+-------------------------------------------------------------------------+
; tco                                                                     ;
+-------+--------------+------------+--------------+---------+------------+
; Slack ; Required tco ; Actual tco ; From         ; To      ; From Clock ;
+-------+--------------+------------+--------------+---------+------------+
; N/A   ; None         ; 7.386 ns   ; LEDR[1]~reg0 ; LEDR[0] ; clc        ;
; N/A   ; None         ; 7.105 ns   ; LEDG[0]~reg0 ; LEDG[0] ; clc        ;
; N/A   ; None         ; 6.867 ns   ; HEX0[2]~reg0 ; HEX0[2] ; clc        ;
; N/A   ; None         ; 6.855 ns   ; HEX0[0]~reg0 ; HEX0[0] ; clc        ;
; N/A   ; None         ; 6.823 ns   ; HEX0[1]~reg0 ; HEX0[1] ; clc        ;
; N/A   ; None         ; 6.627 ns   ; LEDR[1]~reg0 ; LEDR[1] ; clc        ;
; N/A   ; None         ; 6.607 ns   ; HEX0[4]~reg0 ; HEX0[4] ; clc        ;
; N/A   ; None         ; 6.604 ns   ; HEX0[3]~reg0 ; HEX0[3] ; clc        ;
; N/A   ; None         ; 6.596 ns   ; HEX0[6]~reg0 ; HEX0[6] ; clc        ;
; N/A   ; None         ; 6.592 ns   ; HEX0[5]~reg0 ; HEX0[5] ; clc        ;
; N/A   ; None         ; 6.582 ns   ; LEDG[1]~reg0 ; LEDG[1] ; clc        ;
+-------+--------------+------------+--------------+---------+------------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Fri Jul 11 22:20:19 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off Traffic -c Traffic --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clc" is an undefined clock
Warning: Found 1 node(s) in clock paths which may be acting as ripple and/or gated clocks -- node(s) analyzed as buffer(s) resulting in clock skew
    Info: Detected ripple clock "count[25]" as buffer
Info: Clock "clc" has Internal fmax of 220.75 MHz between source register "period[2]" and destination register "HEX0[5]~reg0" (period= 4.53 ns)
    Info: + Longest register to register delay is 0.862 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X31_Y1_N31; Fanout = 11; REG Node = 'period[2]'
        Info: 2: + IC(0.358 ns) + CELL(0.420 ns) = 0.778 ns; Loc. = LCCOMB_X31_Y1_N6; Fanout = 1; COMB Node = 'WideOr1~62'
        Info: 3: + IC(0.000 ns) + CELL(0.084 ns) = 0.862 ns; Loc. = LCFF_X31_Y1_N7; Fanout = 1; REG Node = 'HEX0[5]~reg0'
        Info: Total cell delay = 0.504 ns ( 58.47 % )
        Info: Total interconnect delay = 0.358 ns ( 41.53 % )
    Info: - Smallest clock skew is -3.454 ns
        Info: + Shortest clock path from clock "clc" to destination register is 2.710 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clc'
            Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clc~clkctrl'
            Info: 3: + IC(1.056 ns) + CELL(0.537 ns) = 2.710 ns; Loc. = LCFF_X31_Y1_N7; Fanout = 1; REG Node = 'HEX0[5]~reg0'
            Info: Total cell delay = 1.536 ns ( 56.68 % )
            Info: Total interconnect delay = 1.174 ns ( 43.32 % )
        Info: - Longest clock path from clock "clc" to source register is 6.164 ns
            Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clc'
            Info: 2: + IC(1.908 ns) + CELL(0.787 ns) = 3.694 ns; Loc. = LCFF_X32_Y1_N25; Fanout = 2; REG Node = 'count[25]'
            Info: 3: + IC(0.893 ns) + CELL(0.000 ns) = 4.587 ns; Loc. = CLKCTRL_G14; Fanout = 4; COMB Node = 'count[25]~clkctrl'
            Info: 4: + IC(1.040 ns) + CELL(0.537 ns) = 6.164 ns; Loc. = LCFF_X31_Y1_N31; Fanout = 11; REG Node = 'period[2]'
            Info: Total cell delay = 2.323 ns ( 37.69 % )
            Info: Total interconnect delay = 3.841 ns ( 62.31 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Micro setup delay of destination is -0.036 ns
Info: tco from clock "clc" to destination pin "LEDR[0]" through register "LEDR[1]~reg0" is 7.386 ns
    Info: + Longest clock path from clock "clc" to source register is 2.710 ns
        Info: 1: + IC(0.000 ns) + CELL(0.999 ns) = 0.999 ns; Loc. = PIN_N2; Fanout = 2; CLK Node = 'clc'
        Info: 2: + IC(0.118 ns) + CELL(0.000 ns) = 1.117 ns; Loc. = CLKCTRL_G2; Fanout = 35; COMB Node = 'clc~clkctrl'
        Info: 3: + IC(1.056 ns) + CELL(0.537 ns) = 2.710 ns; Loc. = LCFF_X32_Y1_N27; Fanout = 2; REG Node = 'LEDR[1]~reg0'
        Info: Total cell delay = 1.536 ns ( 56.68 % )
        Info: Total interconnect delay = 1.174 ns ( 43.32 % )
    Info: + Micro clock to output delay of source is 0.250 ns
    Info: + Longest register to pin delay is 4.426 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X32_Y1_N27; Fanout = 2; REG Node = 'LEDR[1]~reg0'
        Info: 2: + IC(1.608 ns) + CELL(2.818 ns) = 4.426 ns; Loc. = PIN_AE23; Fanout = 0; PIN Node = 'LEDR[0]'
        Info: Total cell delay = 2.818 ns ( 63.67 % )
        Info: Total interconnect delay = 1.608 ns ( 36.33 % )
Info: Quartus II Classic Timing Analyzer was successful. 0 errors, 2 warnings
    Info: Allocated 115 megabytes of memory during processing
    Info: Processing ended: Fri Jul 11 22:20:20 2008
    Info: Elapsed time: 00:00:01