traffic.map.rpt

使用ALTERA上DE2平台

; Suppress Register Optimization Related Messages                                ; Off                ; Off                ;
; Number of Removed Registers Reported in Synthesis Report                       ; 100                ; 100                ;
; Clock MUX Protection                                                           ; On                 ; On                 ;
; Block Design Naming                                                            ; Auto               ; Auto               ;
+--------------------------------------------------------------------------------+--------------------+--------------------+


+--------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Source Files Read                                                                             ;
+----------------------------------+-----------------+------------------------+--------------------------------------+
; File Name with User-Entered Path ; Used in Netlist ; File Type              ; File Name with Absolute Path         ;
+----------------------------------+-----------------+------------------------+--------------------------------------+
; Traffic.v                        ; yes             ; User Verilog HDL File  ; D:/PROGRAMING/fpga/Traffic/Traffic.v ;
+----------------------------------+-----------------+------------------------+--------------------------------------+


+-----------------------------------------------------+
; Analysis & Synthesis Resource Usage Summary         ;
+---------------------------------------------+-------+
; Resource                                    ; Usage ;
+---------------------------------------------+-------+
; Estimated Total logic elements              ; 40    ;
;                                             ;       ;
; Total combinational functions               ; 39    ;
; Logic element usage by number of LUT inputs ;       ;
;     -- 4 input functions                    ; 1     ;
;     -- 3 input functions                    ; 11    ;
;     -- <=2 input functions                  ; 27    ;
;                                             ;       ;
; Logic elements by mode                      ;       ;
;     -- normal mode                          ; 15    ;
;     -- arithmetic mode                      ; 24    ;
;                                             ;       ;
; Total registers                             ; 40    ;
;     -- Dedicated logic registers            ; 40    ;
;     -- I/O registers                        ; 0     ;
;                                             ;       ;
; I/O pins                                    ; 13    ;
; Maximum fan-out node                        ; clc   ;
; Maximum fan-out                             ; 36    ;
; Total fan-out                               ; 183   ;
; Average fan-out                             ; 1.99  ;
+---------------------------------------------+-------+


+-----------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Analysis & Synthesis Resource Utilization by Entity                                                                                                                         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
; |Traffic                   ; 39 (39)           ; 40 (40)      ; 0           ; 0            ; 0       ; 0         ; 13   ; 0            ; |Traffic            ; work         ;
+----------------------------+-------------------+--------------+-------------+--------------+---------+-----------+------+--------------+---------------------+--------------+
Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.


+------------------------------------------------------------------+
; Registers Removed During Synthesis                               ;
+---------------------------------------+--------------------------+
; Register name                         ; Reason for Removal       ;
+---------------------------------------+--------------------------+
; LEDR[0]~reg0                          ; Merged with LEDR[1]~reg0 ;
; Total Number of Removed Registers = 1 ;                          ;
+---------------------------------------+--------------------------+


+------------------------------------------------------+
; General Register Statistics                          ;
+----------------------------------------------+-------+
; Statistic                                    ; Value ;
+----------------------------------------------+-------+
; Total registers                              ; 40    ;
; Number of registers using Synchronous Clear  ; 0     ;
; Number of registers using Synchronous Load   ; 0     ;
; Number of registers using Asynchronous Clear ; 4     ;
; Number of registers using Asynchronous Load  ; 0     ;
; Number of registers using Clock Enable       ; 0     ;
; Number of registers using Preset             ; 0     ;
+----------------------------------------------+-------+


+--------------------------------------------------+
; Inverted Register Statistics                     ;
+----------------------------------------+---------+
; Inverted Register                      ; Fan out ;
+----------------------------------------+---------+
; LEDR[1]~reg0                           ; 2       ;
; LEDG[0]~reg0                           ; 1       ;
; Total number of inverted registers = 2 ;         ;
+----------------------------------------+---------+


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Fri Jul 11 22:19:13 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off Traffic -c Traffic
Warning (10227): Verilog HDL Port Declaration warning at Traffic.v(12): data type declaration for "LEDR" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at Traffic.v(16): "LEDR" is declared here
Warning (10227): Verilog HDL Port Declaration warning at Traffic.v(13): data type declaration for "LEDG" declares packed dimensions but the port declaration declaration does not
Info (10151): Verilog HDL Declaration information at Traffic.v(17): "LEDG" is declared here
Info: Found 1 design units, including 1 entities, in source file Traffic.v
    Info: Found entity 1: Traffic
Info: Elaborating entity "Traffic" for the top level hierarchy
Warning (10855): Verilog HDL warning at Traffic.v(22): initial value for variable period should be constant
Info: Duplicate registers merged to single register
    Info: Duplicate register "LEDR[0]~reg0" merged to single register "LEDR[1]~reg0"
Info: Implemented 54 device resources after synthesis - the final resource count might be different
    Info: Implemented 2 input pins
    Info: Implemented 11 output pins
    Info: Implemented 41 logic cells
Info: Quartus II Analysis & Synthesis was successful. 0 errors, 3 warnings
    Info: Allocated 143 megabytes of memory during processing
    Info: Processing ended: Fri Jul 11 22:19:16 2008
    Info: Elapsed time: 00:00:03