flashrdcon.v

用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制

// flashRdCon.v
module flashRdCon(
    clk24M,
    arst,
    callbackbegin,
    pagefull,
    cmdstart,
    cmdfinish,
    datastart,
    addr,
    finish
    );

input
    clk24M,
    arst,
    callbackbegin,
    pagefull,
    cmdfinish;
output
    cmdstart,
    datastart,
    finish;
output [15:0]
    addr;
reg
    cmdstart,
    datastart;
reg [15:0]
    addr;
wire
    addrfull;
reg [2:0]
	state;

assign finish = state[2] & state[1] & state[0];

always @(posedge clk24M or negedge arst)
begin
    if(arst == 0)
    begin
        state <= 3'd0;
        cmdstart <= 1'b0;
        datastart <= 1'b0;
    end
    else
    begin
        case(state)
        3'd0:
            state[0] <= callbackbegin;
        3'd1:
        begin            
            cmdstart <= 1'b1;
            state <= 3'd2;
        end
        3'd2:
        begin
            cmdstart <= 1'b0;
            state[0] <= cmdfinish;
        end
        3'd3:
        begin            
            datastart <= 1'b1;
            state <= 3'd4;
        end
        3'd4:
        begin
            datastart <= 1'b0;
            state[1] <= pagefull;
        end
        3'd6:
        begin
            if(addrfull)//为1时表示没满
            begin
                state <= 3'd1;
            end
            else
            begin
                state <= 3'd7;//结束状态
            end
        end
        endcase
    end
end
//计算读flash的页数
always @(posedge clk24M or negedge arst)
begin
    if(arst == 0)
    begin
        addr <= 16'd0;
    end
    else
    begin
        if(pagefull)
        begin
            addr <= addr + 1'b1;
        end
    end
end
assign addrfull = (((addr[15] | addr[14]) | (addr[13] | addr[12])) | ((addr[11] | addr[10]) | (addr[9] | addr[8]))) |
                (((addr[7] | addr[6]) | (addr[5] | (~addr[4]))) | ((addr[3] | addr[2]) | (addr[1] | (addr[0]))));
endmodule