writecmd.v

用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制

/*module writeCmd(
	clk16M,
	arst,
	start,
	finish,
	cle,
	we,
	ale,
	dataout
	);
	
	input
		clk16M,
		arst,
		start;
	output
		cle,
		we,
		ale,
		finish;
	output [7:0]
		dataout;
	
	reg
		cle,
		we,
		ale,
		finish;
	reg [3:0]
		state;
	reg [7:0]
		dataout;
		
	always @(posedge clk16M or negedge arst)
	begin
		if(arst == 0)
		begin
			cle <= 1'b0;
			we <= 1'b1;
			ale <= 1'b0;
			dataout <= 8'd0;
		end
		else
		begin
			case(state)
			4'd1:
				begin
					cle <= 1'b1;

				end
			4'd2:
				begin
					we <= 1'b0;
					dataout <= 8'h80;	//写命令
				end
			4'd3:
				begin
					we <= 1'b1;
				end
			4'd4:
				begin
					cle <= 1'b0;
					ale <= 1'b1;
				end
			4'd5:
				begin
					we <= 1'b0;
					dataout <= 8'h00;	//写列地址
				end
			4'd6:
				begin
					we <= 1'b1;
				end
			4'd7:
				begin
					we <= 1'b0;
					dataout <= 8'h00;	//写行地址1
				end
			4'd8:
				begin
					we <= 1'b1;
				end
			4'd9:
				begin
					we <= 1'b0;
					dataout <= 8'h00;	//写行地址2
				end
			4'd10:
				begin
					we <= 1'b1;
				end
			4'd11:
				begin
					ale <= 1'b0;
				end
			endcase
		end//else if(rb == 1)
	end//always
	
	always @(posedge clk16M or negedge arst)
	begin
		if(arst == 0)
		begin
			finish <= 1'b0;
		end
		else
		begin
			finish <= (~state[0] & state[1] ) & (state[2] & state[3] );
		end
	end
	
	always @(posedge clk16M or negedge arst)
	begin
		if(arst == 0)
		begin
			state <= 4'd0;
		end
		else
		begin
			case(state)
			4'd0:
				state[0] <= start;
			4'd1:
				state <= 4'd2;
			4'd2:
				state <= 4'd3;
			4'd3:
				state <= 4'd4;
			4'd4:
				state <= 4'd5;
			4'd5:
				state <= 4'd6;
			4'd6:
				state <= 4'd7;
			4'd7:
				state <= 4'd8;
			4'd8:
				state <= 4'd9;
			4'd9:
				state <= 4'd10;
			4'd10:
				state <= 4'd11;
			4'd11:
				state <= 4'd12;
			4'd12:
				state <= 4'd13;
			4'd13:
				state <= 4'd14;
			4'd14:
				state <= 4'd15;
			4'd15:
				state <= 4'd0;
			endcase
		end//else if(start == 1)
	end//always
endmodule*/
module writeCmd(
	clk24M,
	arst,
    addr,
	cmdstart,
	cmdfinish,
	cmdwe,
	cmdcle,
	cmdale,
	sel,
	cmdata
	);
	
	input
		clk24M,
		arst,
		cmdstart;
    input [15:0]
        addr;
	output
		cmdfinish,
		cmdwe,
		cmdcle,
		cmdale,
		sel;
	output [7:0]
		cmdata;
	reg
		cmdfinish,
		cmdwe,
		cmdcle,
		cmdale,
		sel;
	reg [7:0]
		cmdata;
	reg [3:0]
		state;

	always @(posedge clk24M or negedge arst)
	begin
		if(arst == 0)
		begin
			//cmdcle <= 1'b0;
			//cmdwe <= 1'b1;
			//sel <= 1'b0;
			//cmdale <= 1'b0;
			cmdata <= 8'd0;
		end
		else
		begin
			case(state)
			//4'd1:
			//begin
				//cmdcle <= 1'b1;
				//sel <= 1'b0;
			//end
			4'd2:
			begin
				//cmdwe <= 1'b0;
				cmdata <= 8'h80;	//写命令
			end
			//4'd3:
			//begin
				//cmdwe <= 1'b1;
			//end
			//4'd4:
			//begin
				//cmdcle <= 1'b0;
				//cmdale <= 1'b1;
			//end
			4'd5:
			begin
				//cmdwe <= 1'b0;
				cmdata <= 8'h00;	//写列地址
			end
			//4'd6:
			//begin
				//cmdwe <= 1'b1;
			//end
			4'd7:
			begin
				//cmdwe <= 1'b0;
				cmdata <= addr[7:0];//8'h00;	//写行地址1
			end
			//4'd8:
			//begin
				//cmdwe <= 1'b1;
			//end
			4'd9:
			begin
				//cmdwe <= 1'b0;
				cmdata <= addr[15:8];//8'h00;	//写行地址2
			end
			//4'd10:
			//begin
				//cmdwe <= 1'b1;
			//end
			//4'd11:
			//begin
				//cmdale <= 1'b0;
				//sel <= 1'b1;
			//end
			endcase
		end//else if(rb == 1)
	end//always
	always @(posedge clk24M or negedge arst)
    begin
        if(arst == 0)
        begin
            cmdcle <= 1'b0;
        end
        else
        begin
            cmdcle <= (~(state[3] | state[2])) & (state[1] | state[0]);//从1状态到7状态统统cle置高 0011
            /*case(state)
            4'd1:
                cmdcle <= 1'b1;
            4'd4:
                cmdcle <= 1'b0;
            endcase*/
        end
    end
    always @(posedge clk24M or negedge arst)
    begin
        if(arst == 0)
        begin
            sel <= 1'b0;
        end
        else
        begin
            sel <= (state[3] & state[1] & state[0]) | (~((state[3] | state[2]) | (state[1] | state[0])));//1x11 0000
            /*case(state)
            4'd1:
                sel <= 1'b0;
            4'd11:
                sel <= 1'b1;    
            endcase*/
        end
    end
    always @(posedge clk24M or negedge arst)
    begin
        if(arst == 0)
        begin
            cmdale <= 1'b0;
        end
        else
        begin
            cmdale <= (state[2] | (state[3] & (~state[1]))) | (state[3] & state[1] & (~state[0]));
            /*case(state)
            4'd4:
                cmdale <= 1'b1;
            4'd11:
                cmdale <= 1'b0;
            endcase*/
        end
    end
    always @(posedge clk24M or negedge arst)
    begin
        if(arst == 0)
        begin
            cmdwe <= 1'b1;
        end
        else
        begin
            cmdwe <= ((~(state[0] | state[1])) | (~state[3] & (~state[2]) & state[0])) | ((state[3] & state[1]) | (state[2] & state[1] & (~state[0])) | (state[3] & state[2]));
            //cmdwe <= ((state[3] & state[2]) | (state[3] & (~state[2]) &(state[1]|state[0])) | ((~state[3]) & state[2] & state[0]) | ((~state[3]) & (~state[2]) & (~state[0])));
            /*case(state) //xx00 00x1 1x1x x110
                4'd1: //0001
                    cmdwe <= 1'b0;  1
                4'd2: //0010
                    cmdwe <= 1'b1;  0
                4'd3: //0011
                    cmdwe <= 1'b0;  1
                4'd5: //0101
                    cmdwe <= 1'b1;  0
                4'd6: //0110
                    cmdwe <= 1'b0;  1
                4'd7: //0111
                    cmdwe <= 1'b1;  0
                4'd8: //1000
                    cmdwe <= 1'b0;  1
                4'd9: //1001
                    cmdwe <= 1'b1;  0
                4'd10: //1010
                    cmdwe <= 1'b1;   1              
            endcase*/
        end
    end
	always @(posedge clk24M or negedge arst)
	begin
		if(arst == 0)
		begin
			cmdfinish <= 1'b0;
		end
		else
		begin
			cmdfinish <= (state[0] & state[1] ) & (~state[2] & state[3] );//1011
		end
	end
	
	always @(posedge clk24M or negedge arst)
	begin
		if(arst == 0)
		begin
			state <= 4'd0;
		end
		else
		begin
			case(state)
			4'd0:
				state[0] <= cmdstart;
			4'd1:
				state <= 4'd2;
			4'd2:
				state <= 4'd3;
			4'd3:
				state <= 4'd4;
			4'd4:
				state <= 4'd5;
			4'd5:
				state <= 4'd6;
			4'd6:
				state <= 4'd7;
			4'd7:
				state <= 4'd8;
			4'd8:
				state <= 4'd9;
			4'd9:
				state <= 4'd10;
			4'd10:
				state <= 4'd11;
			4'd11:
				state <= 4'd0;
			endcase
		end//else if(start == 1)
	end//always
	
endmodule