flashwrcon.v

用Verilog语言编写的实现NAND Flash块的控制存取以及同步的FIFO的控制

/*module flashWrCon(
	clk16M,
	arst,
	finish,
	start,
	enable,
	dataout,
	wrdfinish
	);
	
	input
		clk16M,
		arst,
		finish;
	output
		start,
		enable,
		wrdfinish;
	output [7:0]
		dataout;
		
	reg
		start,
		enable,
		wrdfinish;
	reg [1:0]
		cnt;
	reg [10:0]
		count;
		
	wire
		s;

	assign dataout = 8'h7e;
	
	always @(posedge clk16M or negedge arst)
	begin
		if(arst == 0)
		begin
			wrdfinish <= 1'b0;
		end
		else
		begin
			wrdfinish <= ~((((~count[10] | count[9]) | (count[8] | count[7])) | ((count[6] | ~count[5]) |
						(count[4] | count[3]))) | ((count[2] | count[1]) | count[0]));
		end
	end
	
	always @(posedge clk16M or negedge arst)
	begin
		if(arst == 0)
		begin
			cnt <= 2'd0;
		end
		else
		begin
			if(s == 0)
			begin
				cnt <= cnt + 1'b1;
			end
		end
	end//always

	assign s = cnt[0] & cnt[1];
	
	always @(posedge clk16M or negedge arst)
	begin
		if(arst == 0)
		begin
			start <= 1'b0;
		end
		else
		begin
			start <= ~cnt[0] & cnt[1];
		end
	end

	always @(posedge clk16M or negedge arst)
	begin
		if(arst == 0)
		begin
			enable <= 1'b0;
		end
		else
		begin
			if(finish == 1)
			begin
				enable <= 1'b1;
			end
			else if(count == 11'd1055)
			begin
				enable <= 1'b0;
			end
		end
	end//always
	
	always @(posedge clk16M or negedge arst)
	begin
		if(arst == 0)
		begin
			count <= 11'd0;
		end
		else
		begin
			if(enable == 1)
			begin
				count <= count + 1'b1;
			end
			else
			begin
				count <= 11'd0;
			end
		end//else
	end//always
		
endmodule*/
module flashWrCon(
	clk24M,
	arst,
    rb,
    AFULL,
	cmdstart,
	cmdfinish,
	datastart,
    addr,
    datafinish
	);
	
input
	clk24M,
	arst,
    rb,
    AFULL,
	cmdfinish,
    datafinish;
output
	cmdstart,
	datastart;
output [15:0]
    addr;
reg
	cmdstart,
	datastart,
    //rbreg,
    //rbpos,
    datafinishreg,
    datafinishpos,
    afullreg,
    afullpos;
reg [2:0]
	state;
reg [15:0]
    addr;
reg [13:0]
    cnt;

/*always @(posedge clk24M or negedge arst)
begin
    if(arst == 0)
    begin
        rbreg <= 1'b0;
        rbpos <= 1'b0;
    end
    else
    begin
        rbreg <= rb;
        rbpos <= ~rbreg & rb;
    end
end	*/

always @(posedge clk24M or negedge arst)
begin
    if(arst == 0)
    begin
        datafinishreg <= 1'b0;
        datafinishpos <= 1'b0;
    end
    else
    begin
        datafinishreg <= datafinish;
        datafinishpos <= (~datafinishreg) & datafinish;
    end
end
        

always @(posedge clk24M or negedge arst)
begin
	if(arst == 0)
	begin
		cmdstart <= 1'b0;
		datastart <= 1'b0;
	end
	else
	begin
        cmdstart <= (~state[1]) & state[0];
        datastart <= state[1] & state[0];
		/*case(state)
		3'd1:
			cmdstart <= 1'b1;
		3'd2:
			cmdstart <= 1'b0;
		3'd3:
			datastart <= 1'b1;
		3'd4:
			datastart <= 1'b0;
		endcase*/
	end
end
always @(posedge clk24M or negedge arst)
begin
    if(arst == 0)
    begin
        afullreg <= 1'b0;
        afullpos <= 1'b0;
    end
    else
    begin
        afullreg <= AFULL;
        afullpos <= ~afullreg & AFULL;
    end
end
always @(posedge clk24M or negedge arst)
begin
	if(arst == 0)
	begin
		state <= 3'd0;
        cnt <= 14'b0;
	end
	else
	begin
		case(state)
		3'd0:
			state[0] <= afullpos | AFULL;//?
		3'd1:
			state <= 3'd2;
		3'd2:
			state[0] <= cmdfinish;
		3'd3:
			state <= 3'd4;
		3'd4:
			state[1] <= datafinishpos;
        3'd6:
        begin
            if(cnt[13]&rb)
            begin
                cnt <= 14'b0;
                state <= 3'd0;
            end
            else if(!cnt[13])
            begin
                cnt <= cnt + 1'b1;
            end
        end

		endcase
	end
end
always @(posedge clk24M or negedge arst)
begin
    if(arst == 0)
    begin
        addr <= 16'Hffff;
    end
    else
    begin
        if(cmdstart)
        begin
            addr <= addr + 1'b1;
        end
    end
end

endmodule