lpm_abs_ur9.tdf

用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行

--lpm_abs CARRY_CHAIN="MANUAL" DEVICE_FAMILY="Cyclone II" IGNORE_CARRY_BUFFERS="OFF" LPM_WIDTH=21 data result
--VERSION_BEGIN 7.2SP3 cbx_cycloneii 2007:06:13:15:47:32:SJ cbx_lpm_abs 2006:04:25:14:52:42:SJ cbx_lpm_add_sub 2007:08:06:16:01:34:SJ cbx_mgl 2007:08:03:15:48:12:SJ cbx_stratix 2007:10:18:20:36:46:SJ cbx_stratixii 2007:10:19:15:30:42:SJ cbx_util_mgl 2007:11:07:17:40:20:SJ  VERSION_END


-- Copyright (C) 1991-2007 Altera Corporation
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--  and other software and tools, and its AMPP partner logic 
--  functions, and any output files from any of the foregoing 
--  (including device programming or simulation files), and any 
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--  to the terms and conditions of the Altera Program License 
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--  Agreement, or other applicable license agreement, including, 
--  without limitation, that your use is for the sole purpose of 
--  programming logic devices manufactured by Altera and sold by 
--  Altera or its authorized distributors.  Please refer to the 
--  applicable agreement for further details.


FUNCTION carry_sum (cin, sin)
RETURNS ( cout, sout);

--synthesis_resources = lut 21 
SUBDESIGN lpm_abs_ur9
( 
	data[20..0]	:	input;
	overflow	:	output;
	result[20..0]	:	output;
) 
VARIABLE 
	cs1a[20..0] : carry_sum;
	result_tmp[20..0]	: WIRE;

BEGIN 
	cs1a[].cin = ( ((data[20..20] $ data[20..1]) & cs1a[19..0].cout), ((! data[0..0]) & data[20..20]));
	cs1a[].sin = ( ((data[20..20] $ data[20..1]) $ cs1a[19..0].cout), data[0..0]);
	overflow = (result_tmp[20..20] & data[20..20]);
	result[] = result_tmp[];
	result_tmp[] = ( cs1a[20..1].sout, data[0..0]);
END;
--VALID FILE