smallkeybaord.tan.rpt

用verilog写的4*4小键盘按键检测程序。本工程已经编译好。可以直接在Atera DE1 Fpga开发板上运行

; N/A           ; None        ; -3.915 ns ; GPIO2[1] ; LEDG[0]~reg0 ; clk      ;
; N/A           ; None        ; -6.823 ns ; GPIO2[0] ; LEDG[3]~reg0 ; clk      ;
; N/A           ; None        ; -6.837 ns ; GPIO2[0] ; LEDG[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.011 ns ; GPIO2[1] ; LEDG[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.025 ns ; GPIO2[1] ; LEDG[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.357 ns ; GPIO2[3] ; LEDG[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.371 ns ; GPIO2[3] ; LEDG[2]~reg0 ; clk      ;
; N/A           ; None        ; -7.425 ns ; GPIO2[2] ; LEDG[3]~reg0 ; clk      ;
; N/A           ; None        ; -7.439 ns ; GPIO2[2] ; LEDG[2]~reg0 ; clk      ;
+---------------+-------------+-----------+----------+--------------+----------+


+--------------------------+
; Timing Analyzer Messages ;
+--------------------------+
Info: *******************************************************************
Info: Running Quartus II Classic Timing Analyzer
    Info: Version 7.2 Build 207 03/18/2008 Service Pack 3 SJ Full Version
    Info: Processing started: Fri Jul 04 10:21:55 2008
Info: Command: quartus_tan --read_settings_files=off --write_settings_files=off smallkeybaord -c smallkeybaord --timing_analysis_only
Warning: Found pins functioning as undefined clocks and/or memory enables
    Info: Assuming node "clk" is an undefined clock
Info: Clock "clk" has Internal fmax of 142.78 MHz between source register "i[15]" and destination register "LEDG[3]~reg0" (period= 7.004 ns)
    Info: + Longest register to register delay is 6.771 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X19_Y18_N17; Fanout = 3; REG Node = 'i[15]'
        Info: 2: + IC(1.199 ns) + CELL(0.450 ns) = 1.649 ns; Loc. = LCCOMB_X21_Y17_N18; Fanout = 1; COMB Node = 'i[12]~450'
        Info: 3: + IC(0.300 ns) + CELL(0.491 ns) = 2.440 ns; Loc. = LCCOMB_X21_Y17_N30; Fanout = 9; COMB Node = 'i[12]~451'
        Info: 4: + IC(0.488 ns) + CELL(0.178 ns) = 3.106 ns; Loc. = LCCOMB_X20_Y17_N20; Fanout = 24; COMB Node = 'i[12]~452'
        Info: 5: + IC(0.574 ns) + CELL(0.178 ns) = 3.858 ns; Loc. = LCCOMB_X20_Y17_N8; Fanout = 2; COMB Node = 'Add0~1813'
        Info: 6: + IC(1.435 ns) + CELL(0.278 ns) = 5.571 ns; Loc. = LCCOMB_X21_Y17_N14; Fanout = 6; COMB Node = 'WideOr0~138'
        Info: 7: + IC(0.311 ns) + CELL(0.322 ns) = 6.204 ns; Loc. = LCCOMB_X21_Y17_N22; Fanout = 1; COMB Node = 'Add1~156'
        Info: 8: + IC(0.293 ns) + CELL(0.178 ns) = 6.675 ns; Loc. = LCCOMB_X21_Y17_N16; Fanout = 1; COMB Node = 'LEDG~76'
        Info: 9: + IC(0.000 ns) + CELL(0.096 ns) = 6.771 ns; Loc. = LCFF_X21_Y17_N17; Fanout = 1; REG Node = 'LEDG[3]~reg0'
        Info: Total cell delay = 2.171 ns ( 32.06 % )
        Info: Total interconnect delay = 4.600 ns ( 67.94 % )
    Info: - Smallest clock skew is 0.006 ns
        Info: + Shortest clock path from clock "clk" to destination register is 2.828 ns
            Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.982 ns) + CELL(0.602 ns) = 2.828 ns; Loc. = LCFF_X21_Y17_N17; Fanout = 1; REG Node = 'LEDG[3]~reg0'
            Info: Total cell delay = 1.608 ns ( 56.86 % )
            Info: Total interconnect delay = 1.220 ns ( 43.14 % )
        Info: - Longest clock path from clock "clk" to source register is 2.822 ns
            Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'
            Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'
            Info: 3: + IC(0.976 ns) + CELL(0.602 ns) = 2.822 ns; Loc. = LCFF_X19_Y18_N17; Fanout = 3; REG Node = 'i[15]'
            Info: Total cell delay = 1.608 ns ( 56.98 % )
            Info: Total interconnect delay = 1.214 ns ( 43.02 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Micro setup delay of destination is -0.038 ns
Info: tsu for register "LEDG[2]~reg0" (data pin = "GPIO2[2]", clock pin = "clk") is 7.687 ns
    Info: + Longest pin to register delay is 10.553 ns
        Info: 1: + IC(0.000 ns) + CELL(0.874 ns) = 0.874 ns; Loc. = PIN_E22; Fanout = 3; PIN Node = 'GPIO2[2]'
        Info: 2: + IC(5.598 ns) + CELL(0.545 ns) = 7.017 ns; Loc. = LCCOMB_X49_Y15_N4; Fanout = 2; COMB Node = 'LEDG[2]~74'
        Info: 3: + IC(2.919 ns) + CELL(0.521 ns) = 10.457 ns; Loc. = LCCOMB_X20_Y17_N12; Fanout = 1; COMB Node = 'LEDG~75'
        Info: 4: + IC(0.000 ns) + CELL(0.096 ns) = 10.553 ns; Loc. = LCFF_X20_Y17_N13; Fanout = 1; REG Node = 'LEDG[2]~reg0'
        Info: Total cell delay = 2.036 ns ( 19.29 % )
        Info: Total interconnect delay = 8.517 ns ( 80.71 % )
    Info: + Micro setup delay of destination is -0.038 ns
    Info: - Shortest clock path from clock "clk" to destination register is 2.828 ns
        Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.982 ns) + CELL(0.602 ns) = 2.828 ns; Loc. = LCFF_X20_Y17_N13; Fanout = 1; REG Node = 'LEDG[2]~reg0'
        Info: Total cell delay = 1.608 ns ( 56.86 % )
        Info: Total interconnect delay = 1.220 ns ( 43.14 % )
Info: tco from clock "clk" to destination pin "LEDG[3]" through register "LEDG[3]~reg0" is 9.830 ns
    Info: + Longest clock path from clock "clk" to source register is 2.828 ns
        Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'
        Info: 3: + IC(0.982 ns) + CELL(0.602 ns) = 2.828 ns; Loc. = LCFF_X21_Y17_N17; Fanout = 1; REG Node = 'LEDG[3]~reg0'
        Info: Total cell delay = 1.608 ns ( 56.86 % )
        Info: Total interconnect delay = 1.220 ns ( 43.14 % )
    Info: + Micro clock to output delay of source is 0.277 ns
    Info: + Longest register to pin delay is 6.725 ns
        Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LCFF_X21_Y17_N17; Fanout = 1; REG Node = 'LEDG[3]~reg0'
        Info: 2: + IC(3.875 ns) + CELL(2.850 ns) = 6.725 ns; Loc. = PIN_V21; Fanout = 0; PIN Node = 'LEDG[3]'
        Info: Total cell delay = 2.850 ns ( 42.38 % )
        Info: Total interconnect delay = 3.875 ns ( 57.62 % )
Info: th for register "LEDG[0]~reg0" (data pin = "GPIO2[2]", clock pin = "clk") is -3.597 ns
    Info: + Longest clock path from clock "clk" to destination register is 2.843 ns
        Info: 1: + IC(0.000 ns) + CELL(1.006 ns) = 1.006 ns; Loc. = PIN_D12; Fanout = 1; CLK Node = 'clk'
        Info: 2: + IC(0.238 ns) + CELL(0.000 ns) = 1.244 ns; Loc. = CLKCTRL_G11; Fanout = 40; COMB Node = 'clk~clkctrl'