counter_16_bits.hier_info

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过

|counter_16_bits
Clk_65536Hz => counter_out[14]~reg0.CLK
Clk_65536Hz => counter_out[13]~reg0.CLK
Clk_65536Hz => counter_out[12]~reg0.CLK
Clk_65536Hz => counter_out[11]~reg0.CLK
Clk_65536Hz => counter_out[10]~reg0.CLK
Clk_65536Hz => counter_out[9]~reg0.CLK
Clk_65536Hz => counter_out[8]~reg0.CLK
Clk_65536Hz => counter_out[7]~reg0.CLK
Clk_65536Hz => counter_out[6]~reg0.CLK
Clk_65536Hz => counter_out[5]~reg0.CLK
Clk_65536Hz => counter_out[4]~reg0.CLK
Clk_65536Hz => counter_out[3]~reg0.CLK
Clk_65536Hz => counter_out[2]~reg0.CLK
Clk_65536Hz => counter_out[1]~reg0.CLK
Clk_65536Hz => counter_out[0]~reg0.CLK
Clk_65536Hz => counter_out[15]~reg0.CLK
Reset => ~NO_FANOUT~
counter_out[0] <= counter_out[0]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[1] <= counter_out[1]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[2] <= counter_out[2]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[3] <= counter_out[3]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[4] <= counter_out[4]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[5] <= counter_out[5]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[6] <= counter_out[6]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[7] <= counter_out[7]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[8] <= counter_out[8]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[9] <= counter_out[9]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[10] <= counter_out[10]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[11] <= counter_out[11]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[12] <= counter_out[12]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[13] <= counter_out[13]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[14] <= counter_out[14]~reg0.DB_MAX_OUTPUT_PORT_TYPE
counter_out[15] <= counter_out[15]~reg0.DB_MAX_OUTPUT_PORT_TYPE