counter_16_bits.tan.qmsg

步进电机位置系统 步进电机位置系统block symbol file 步进电机位置系统的Verilog HDL程序设计 已编译通过

{ "Warning" "WTAN_NO_CLOCKS" "" "Warning: Found pins functioning as undefined clocks and/or memory enables" { { "Info" "ITAN_NODE_MAP_TO_CLK" "Clk_65536Hz " "Info: Assuming node \"Clk_65536Hz\" is an undefined clock" {  } { { "counter_16_bits.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/counter_16_bits.v" 6 -1 0 } } { "d:/altera/quartus42/bin/Assignment Editor.qase" "" { Assignment "d:/altera/quartus42/bin/Assignment Editor.qase" 1 { { 0 "Clk_65536Hz" } } } }  } 0}  } {  } 0}
{ "Info" "ITDB_FULL_CLOCK_REG_RESULT" "Clk_65536Hz register lpm_counter:counter_out_rtl_0\|dffs\[0\] register lpm_counter:counter_out_rtl_0\|dffs\[15\] 172.41 MHz 5.8 ns Internal " "Info: Clock \"Clk_65536Hz\" has Internal fmax of 172.41 MHz between source register \"lpm_counter:counter_out_rtl_0\|dffs\[0\]\" and destination register \"lpm_counter:counter_out_rtl_0\|dffs\[15\]\" (period= 5.8 ns)" { { "Info" "ITDB_FULL_DATA_PATH_RESULT" "3.700 ns + Longest register register " "Info: + Longest register to register delay is 3.700 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:counter_out_rtl_0\|dffs\[0\] 1 REG LC17 17 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC17; Fanout = 17; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "" { lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(1.100 ns) + CELL(2.600 ns) 3.700 ns lpm_counter:counter_out_rtl_0\|dffs\[15\] 2 REG LC5 2 " "Info: 2: + IC(1.100 ns) + CELL(2.600 ns) = 3.700 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[15\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "3.700 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "2.600 ns 70.27 % " "Info: Total cell delay = 2.600 ns ( 70.27 % )" {  } {  } 0} { "Info" "ITDB_TOTAL_IC_DELAY" "1.100 ns 29.73 % " "Info: Total interconnect delay = 1.100 ns ( 29.73 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "3.700 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[15] } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_SKEW_RESULT" "0.000 ns - Smallest " "Info: - Smallest clock skew is 0.000 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_65536Hz destination 1.300 ns + Shortest register " "Info: + Shortest clock path from clock \"Clk_65536Hz\" to destination register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clk_65536Hz 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'Clk_65536Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "" { Clk_65536Hz } "NODE_NAME" } "" } } { "counter_16_bits.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/counter_16_bits.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:counter_out_rtl_0\|dffs\[15\] 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[15\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "0.100 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "1.300 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clk_65536Hz Clk_65536Hz~out lpm_counter:counter_out_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_65536Hz source 1.300 ns - Longest register " "Info: - Longest clock path from clock \"Clk_65536Hz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clk_65536Hz 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'Clk_65536Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "" { Clk_65536Hz } "NODE_NAME" } "" } } { "counter_16_bits.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/counter_16_bits.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:counter_out_rtl_0\|dffs\[0\] 2 REG LC17 17 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC17; Fanout = 17; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[0\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "0.100 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "1.300 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clk_65536Hz Clk_65536Hz~out lpm_counter:counter_out_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "1.300 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clk_65536Hz Clk_65536Hz~out lpm_counter:counter_out_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "1.300 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clk_65536Hz Clk_65536Hz~out lpm_counter:counter_out_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_TSU_DELAY" "0.800 ns + " "Info: + Micro setup delay of destination is 0.800 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "3.700 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "3.700 ns" { lpm_counter:counter_out_rtl_0|dffs[0] lpm_counter:counter_out_rtl_0|dffs[15] } { 0.000ns 1.100ns } { 0.000ns 2.600ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "1.300 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clk_65536Hz Clk_65536Hz~out lpm_counter:counter_out_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "1.300 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[0] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clk_65536Hz Clk_65536Hz~out lpm_counter:counter_out_rtl_0|dffs[0] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0}
{ "Info" "ITDB_FULL_TCO_RESULT" "Clk_65536Hz counter_out\[15\] lpm_counter:counter_out_rtl_0\|dffs\[15\] 2.800 ns register " "Info: tco from clock \"Clk_65536Hz\" to destination pin \"counter_out\[15\]\" through register \"lpm_counter:counter_out_rtl_0\|dffs\[15\]\" is 2.800 ns" { { "Info" "ITDB_FULL_CLOCK_PATH_RESULT" "Clk_65536Hz source 1.300 ns + Longest register " "Info: + Longest clock path from clock \"Clk_65536Hz\" to source register is 1.300 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(1.200 ns) 1.200 ns Clk_65536Hz 1 CLK PIN_43 16 " "Info: 1: + IC(0.000 ns) + CELL(1.200 ns) = 1.200 ns; Loc. = PIN_43; Fanout = 16; CLK Node = 'Clk_65536Hz'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "" { Clk_65536Hz } "NODE_NAME" } "" } } { "counter_16_bits.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/counter_16_bits.v" 6 -1 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.100 ns) 1.300 ns lpm_counter:counter_out_rtl_0\|dffs\[15\] 2 REG LC5 2 " "Info: 2: + IC(0.000 ns) + CELL(0.100 ns) = 1.300 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[15\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "0.100 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "1.300 ns 100.00 % " "Info: Total cell delay = 1.300 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "1.300 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clk_65536Hz Clk_65536Hz~out lpm_counter:counter_out_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } }  } 0} { "Info" "ITDB_FULL_TCO_DELAY" "1.300 ns + " "Info: + Micro clock to output delay of source is 1.300 ns" {  } { { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_FULL_DATA_PATH_RESULT" "0.200 ns + Longest register pin " "Info: + Longest register to pin delay is 0.200 ns" { { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.000 ns) 0.000 ns lpm_counter:counter_out_rtl_0\|dffs\[15\] 1 REG LC5 2 " "Info: 1: + IC(0.000 ns) + CELL(0.000 ns) = 0.000 ns; Loc. = LC5; Fanout = 2; REG Node = 'lpm_counter:counter_out_rtl_0\|dffs\[15\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "" { lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "lpm_counter.tdf" "" { Text "d:/altera/quartus42/libraries/megafunctions/lpm_counter.tdf" 262 9 0 } }  } 0} { "Info" "ITDB_NODE_DELAY" "IC(0.000 ns) + CELL(0.200 ns) 0.200 ns counter_out\[15\] 2 PIN PIN_8 0 " "Info: 2: + IC(0.000 ns) + CELL(0.200 ns) = 0.200 ns; Loc. = PIN_8; Fanout = 0; PIN Node = 'counter_out\[15\]'" {  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[15] counter_out[15] } "NODE_NAME" } "" } } { "counter_16_bits.v" "" { Text "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/counter_16_bits.v" 5 -1 0 } }  } 0} { "Info" "ITDB_TOTAL_CELL_DELAY" "0.200 ns 100.00 % " "Info: Total cell delay = 0.200 ns ( 100.00 % )" {  } {  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[15] counter_out[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[15] counter_out[15] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}  } { { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "1.300 ns" { Clk_65536Hz lpm_counter:counter_out_rtl_0|dffs[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "1.300 ns" { Clk_65536Hz Clk_65536Hz~out lpm_counter:counter_out_rtl_0|dffs[15] } { 0.000ns 0.000ns 0.000ns } { 0.000ns 1.200ns 0.100ns } } } { "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" "" { Report "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits_cmp.qrpt" Compiler "counter_16_bits" "UNKNOWN" "V1" "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/db/counter_16_bits.quartus_db" { Floorplan "E:/戴仙金/资料/Verilog书/源代码/step_motor/counter_16_bits/" "" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[15] counter_out[15] } "NODE_NAME" } "" } } { "d:/altera/quartus42/bin/Technology_Viewer.qrui" "" { "Technology Map Viewer" "d:/altera/quartus42/bin/Technology_Viewer.qrui" "0.200 ns" { lpm_counter:counter_out_rtl_0|dffs[15] counter_out[15] } { 0.000ns 0.000ns } { 0.000ns 0.200ns } } }  } 0}
{ "Info" "IQEXE_ERROR_COUNT" "Timing Analyzer 0 s 1  " "Info: Quartus II Timing Analyzer was successful. 0 errors, 1 warning" { { "Info" "IQEXE_END_BANNER_TIME" "Wed Jul 19 20:36:47 2006 " "Info: Processing ended: Wed Jul 19 20:36:47 2006" {  } {  } 0} { "Info" "IQEXE_ELAPSED_TIME" "00:00:02 " "Info: Elapsed time: 00:00:02" {  } {  } 0}  } {  } 0}