eth_wb_an.v

网卡的IP核

// Copyright (C) 1991-2005 Altera Corporation
// Your use of Altera Corporation's design tools, logic functions 
// and other software and tools, and its AMPP partner logic       
// functions, and any output files any of the foregoing           
// (including device programming or simulation files), and any    
// associated documentation or information are expressly subject  
// to the terms and conditions of the Altera Program License      
// Subscription Agreement, Altera MegaCore Function License       
// Agreement, or other applicable license agreement, including,   
// without limitation, that your use is for the sole purpose of   
// programming logic devices manufactured by Altera and sold by   
// Altera or its authorized distributors.  Please refer to the    
// applicable agreement for further details.

module eth_wb_an(
	CLK,
	RESET,
	write,
	chipselect,
	m_waitrequst_n,
	TX_CLK,
	RX_CLK,
	RX_DV,
	RX_ER,
	COL,
	CRS,
	address,
	byteenable,
	m_readdata,
	RXD,
	writedata,
	waitrequst_n,
	m_write,
	TX_EN,
	TX_ER,
	MDC,
	MDDIS,
	irq,
	m_read,
	MDIO,
	m_address,
	m_byteenable,
	m_writedata,
	readdata,
	TXD
);

input	CLK;
input	RESET;
input	write;
input	chipselect;
input	m_waitrequst_n;
input	TX_CLK;
input	RX_CLK;
input	RX_DV;
input	RX_ER;
input	COL;
input	CRS;
input	[11:2] address;
input	[3:0] byteenable;
input	[31:0] m_readdata;
input	[3:0] RXD;
input	[31:0] writedata;
output	waitrequst_n;
output	m_write;
output	TX_EN;
output	TX_ER;
output	MDC;
output	MDDIS;
output	irq;
output	m_read;
inout	MDIO;
output	[31:0] m_address;
output	[3:0] m_byteenable;
output	[31:0] m_writedata;
output	[31:0] readdata;
output	[3:0] TXD;

wire	SYNTHESIZED_WIRE_0;
wire	SYNTHESIZED_WIRE_1;
wire	SYNTHESIZED_WIRE_2;
wire	SYNTHESIZED_WIRE_3;
wire	SYNTHESIZED_WIRE_4;
wire	SYNTHESIZED_WIRE_10;
wire	SYNTHESIZED_WIRE_11;
wire	SYNTHESIZED_WIRE_8;

assign	MDDIS = 0;




eth_top	b2v_inst(.wb_clk_i(CLK),
.wb_rst_i(RESET),.wb_we_i(write),.wb_cyc_i(chipselect),.wb_stb_i(chipselect),.m_wb_ack_i(m_waitrequst_n),.m_wb_err_i(m_waitrequst_n),.mtx_clk_pad_i(TX_CLK),.mrx_clk_pad_i(RX_CLK),.mrxdv_pad_i(RX_DV),.mrxerr_pad_i(RX_ER),.mcoll_pad_i(COL),.mcrs_pad_i(CRS),.md_pad_i(SYNTHESIZED_WIRE_0),.m_wb_dat_i(m_readdata),.mrxd_pad_i(RXD),.wb_adr_i(address),.wb_dat_i(writedata),.wb_sel_i(byteenable),.wb_ack_o(waitrequst_n),.m_wb_we_o(SYNTHESIZED_WIRE_10),.m_wb_cyc_o(SYNTHESIZED_WIRE_3),.m_wb_stb_o(SYNTHESIZED_WIRE_4),.mtxen_pad_o(TX_EN),.mtxerr_pad_o(TX_ER),.mdc_pad_o(MDC),.md_pad_o(SYNTHESIZED_WIRE_1),.md_padoe_o(SYNTHESIZED_WIRE_2),.int_o(irq),.m_wb_adr_o(m_address),.m_wb_dat_o(m_writedata),.m_wb_sel_o(m_byteenable),.mtxd_pad_o(TXD),.wb_dat_o(readdata));
defparam	b2v_inst.Tp = 1;

bidirection_io	b2v_inst2(.in_port(SYNTHESIZED_WIRE_1),
.port_oe(SYNTHESIZED_WIRE_2),.bir_port(MDIO),.out_port(SYNTHESIZED_WIRE_0));
assign	SYNTHESIZED_WIRE_11 = SYNTHESIZED_WIRE_3 & SYNTHESIZED_WIRE_4;
assign	m_write = SYNTHESIZED_WIRE_10 & SYNTHESIZED_WIRE_11;
assign	SYNTHESIZED_WIRE_8 =  ~SYNTHESIZED_WIRE_10;
assign	m_read = SYNTHESIZED_WIRE_8 & SYNTHESIZED_WIRE_11;


endmodule