bidirection_io.v

来自「网卡的IP核」· Verilog 代码 · 共 8 行

module bidirection_io(in_port,out_port,bir_port,port_oe);
input in_port;
output out_port;
inout bir_port;
input port_oe;
assign bir_port=port_oe?in_port:1'bz;
assign out_port=bir_port;
endmodule