class.ptf

网卡的IP核

                  tooltip = "";
                }
              }
            }
          }
        }
      }
      FILE eth_crc.v
      {
        file_mod = "Wed Jan 23 18:28:16 CST 2002";
        quartus_map_start = "Wed Mar 01 15:20:46 CST 2006";
        quartus_map_finished = "Wed Mar 01 15:20:48 CST 2006";
        #found 1 valid modules
        WRAPPER eth_crc
        {
          CLASS eth_crc
          {
            MODULE_DEFAULTS 
            {
              class = "eth_crc";
              class_version = "1.0";
              SYSTEM_BUILDER_INFO 
              {
                Instantiate_In_System_Module = "1";
              }
              SLAVE avalon_slave_0
              {
                SYSTEM_BUILDER_INFO 
                {
                  Bus_Type = "avalon";
                }
                PORT_WIRING 
                {
                  PORT Clk
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT Reset
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT Data
                  {
                    width = "4";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT Enable
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT Initialize
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT Crc
                  {
                    width = "32";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT CrcError
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                }
              }
            }
            USER_INTERFACE 
            {
              USER_LABELS 
              {
                name = "eth_crc";
                technology = "imported components";
              }
            }
            CB_GENERATOR 
            {
              top_module_name = "eth_crc";
              emit_system_h = "0";
              HDL_FILES 
              {
                FILE 
                {
                  filepath = "E:/IP/eth_wb_an/eth_crc.v";
                  use_in_simulation = "1";
                  use_in_synthesis = "1";
                }
              }
            }
            SOPC_Builder_Version = "0.0";
            COMPONENT_BUILDER 
            {
              HDL_PARAMETERS 
              {
                # generated by cbDocument.CBDocument.getParameterContainer:385
                # used only by Component Editor
                HDL_PARAMETER tp
                {
                  parameter_name = "Tp";
                  type = "integer";
                  default_value = "1";
                  editable = "1";
                  tooltip = "";
                }
              }
            }
          }
        }
      }
      FILE eth_defines.v
      {
        file_mod = "Fri Jan 06 11:13:12 CST 2006";
        quartus_map_start = "Wed Mar 01 15:20:49 CST 2006";
        quartus_map_finished = "Wed Mar 01 15:20:51 CST 2006";
        #found 0 valid modules
      }
      FILE eth_fifo.v
      {
        file_mod = "Wed Apr 13 20:18:20 CST 2005";
        quartus_map_start = "Wed Mar 01 15:20:52 CST 2006";
        quartus_map_finished = "Wed Mar 01 15:20:54 CST 2006";
        #found 1 valid modules
        WRAPPER eth_fifo
        {
          CLASS eth_fifo
          {
            MODULE_DEFAULTS 
            {
              class = "eth_fifo";
              class_version = "1.0";
              SYSTEM_BUILDER_INFO 
              {
                Instantiate_In_System_Module = "1";
              }
              SLAVE avalon_slave_0
              {
                SYSTEM_BUILDER_INFO 
                {
                  Bus_Type = "avalon";
                }
                PORT_WIRING 
                {
                  PORT clk
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "clk";
                    is_shared = "0";
                  }
                  PORT reset
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "reset";
                    is_shared = "0";
                  }
                  PORT write
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "write";
                    is_shared = "0";
                  }
                  PORT read
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "read";
                    is_shared = "0";
                  }
                  PORT clear
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT data_in
                  {
                    width = "-1";
                    width_expression = "DATA_WIDTH-1..0";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT data_out
                  {
                    width = "-1";
                    width_expression = "DATA_WIDTH-1..0";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT almost_full
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT full
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT almost_empty
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT empty
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT cnt
                  {
                    width = "-1";
                    width_expression = "CNT_WIDTH-1..0";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                }
              }
            }
            USER_INTERFACE 
            {
              USER_LABELS 
              {
                name = "eth_fifo";
                technology = "imported components";
              }
            }
            CB_GENERATOR 
            {
              top_module_name = "eth_fifo";
              emit_system_h = "0";
              HDL_FILES 
              {
                FILE 
                {
                  filepath = "E:/IP/eth_wb_an/eth_fifo.v";
                  use_in_simulation = "1";
                  use_in_synthesis = "1";
                }
              }
            }
            SOPC_Builder_Version = "0.0";
            COMPONENT_BUILDER 
            {
              HDL_PARAMETERS 
              {
                # generated by cbDocument.CBDocument.getParameterContainer:385
                # used only by Component Editor
                HDL_PARAMETER data_width
                {
                  parameter_name = "DATA_WIDTH";
                  type = "integer";
                  default_value = "32";
                  editable = "1";
                  tooltip = "";
                }
                HDL_PARAMETER depth
                {
                  parameter_name = "DEPTH";
                  type = "integer";
                  default_value = "8";
                  editable = "1";
                  tooltip = "";
                }
                HDL_PARAMETER cnt_width
                {
                  parameter_name = "CNT_WIDTH";
                  type = "integer";
                  default_value = "4";
                  editable = "1";
                  tooltip = "";
                }
                HDL_PARAMETER tp
                {
                  parameter_name = "Tp";
                  type = "integer";
                  default_value = "1";
                  editable = "1";
                  tooltip = "";
                }
              }
            }
          }
        }
      }
      FILE eth_maccontrol.v
      {
        file_mod = "Wed Jan 22 21:49:26 CST 2003";
        quartus_map_start = "Wed Mar 01 15:20:55 CST 2006";
        quartus_map_finished = "Wed Mar 01 15:20:57 CST 2006";
        #found 1 valid modules
        WRAPPER eth_maccontrol
        {
          CLASS eth_maccontrol
          {
            MODULE_DEFAULTS 
            {
              class = "eth_maccontrol";
              class_version = "1.0";
              SYSTEM_BUILDER_INFO 
              {
                Instantiate_In_System_Module = "1";
              }
              SLAVE avalon_slave_0
              {
                SYSTEM_BUILDER_INFO 
                {
                  Bus_Type = "avalon";
                }
                PORT_WIRING 
                {
                  PORT MTxClk
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT MRxClk
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT TxReset
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT RxReset
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT TPauseRq
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT TxDataIn
                  {
                    width = "8";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT TxStartFrmIn
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT TxUsedDataIn
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT TxEndFrmIn
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT TxDoneIn
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT TxAbortIn
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }