class.ptf

网卡的IP核

          direction = "input";
          type = "waitrequest_n";
          is_shared = "0";
        }
        PORT m_readdata
        {
          width = "32";
          width_expression = "";
          direction = "input";
          type = "readdata";
          is_shared = "0";
        }
        PORT m_write
        {
          width = "1";
          width_expression = "";
          direction = "output";
          type = "write";
          is_shared = "0";
        }
        PORT m_read
        {
          width = "1";
          width_expression = "";
          direction = "output";
          type = "read";
          is_shared = "0";
        }
        PORT m_address
        {
          width = "32";
          width_expression = "";
          direction = "output";
          type = "address";
          is_shared = "0";
        }
        PORT m_byteenable
        {
          width = "4";
          width_expression = "";
          direction = "output";
          type = "byteenable";
          is_shared = "0";
        }
        PORT m_writedata
        {
          width = "32";
          width_expression = "";
          direction = "output";
          type = "writedata";
          is_shared = "0";
        }
      }
    }
  }
  USER_INTERFACE 
  {
    USER_LABELS 
    {
      name = "eth_wb_an";
      technology = "Ethernet";
    }
    WIZARD_UI the_wizard_ui
    {
      title = "eth_wb_an - {{ $MOD }}";
      CONTEXT 
      {
        H = "WIZARD_SCRIPT_ARGUMENTS/hdl_parameters";
        M = "";
        SBI_ = "SYSTEM_BUILDER_INFO";
        SBI_avalon_slave_0 = "SLAVE avalon_slave_0/SYSTEM_BUILDER_INFO";
        SBI_avalon_master_0 = "MASTER avalon_master_0/SYSTEM_BUILDER_INFO";
        # The following signals have parameterized widths:
        PORT_address = "SLAVE avalon_slave_0/PORT_WIRING/PORT address";
      }
      PAGES main
      {
        PAGE 1
        {
          align = "left";
          title = "<b>eth_wb_an 1.0</b> Settings";
          layout = "vertical";
          TEXT 
          {
            title = "Built on: 2006.03.01.15:28:11";
          }
          TEXT 
          {
            title = "Class name: eth_wb_an";
          }
          TEXT 
          {
            title = "Class version: 1.0";
          }
          TEXT 
          {
            title = "Component name: eth_wb_an";
          }
          TEXT 
          {
            title = "Component Group: Ethernet";
          }
          GROUP variable_port_widths
          {
            # This group is for display only, to preview parameterized port widths
            title = "Parameterized Signal Widths";
            layout = "form";
            align = "left";
            EDIT address_width
            {
              id = "address_width";
              editable = "0";
              title = "address[11..2]:";
              tooltip = "<b>address[11..2]</b><br> direction: input<br> signal type: address";
              # This expression should emulate the HDL, and assign the port width
              dummy = "{{ $PORT_address/width = (int(11) - int(2) + 1); }}";
              dummy_dummy = "{{ $SBI_avalon_slave_0/Address_Width = $PORT_address/width; }}";
              DATA 
              {
                # The EDIT field is noneditable, so this just reads the current width.
                $PORT_address/width = "$";
              }
              warning = "{{ if($PORT_address/width <= 0)('width of address must be greater than zero' ) }}";
            }
          }
        }
      }
    }
  }
  CB_GENERATOR 
  {
    top_module_name = "eth_wb_an.v:eth_wb_an";
    emit_system_h = "1";
    HDL_FILES 
    {
      FILE 
      {
        filepath = "hdl/bidirection_io.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_clockgen.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_cop.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_crc.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_defines.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_fifo.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_maccontrol.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_macstatus.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_miim.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_outputcontrol.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_random.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_receivecontrol.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_register.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_registers.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_rxaddrcheck.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_rxcounters.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_rxethmac.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_rxstatem.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_shiftreg.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_spram_256x32.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_top.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_transmitcontrol.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_txcounters.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_txethmac.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_txstatem.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_wb_an.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/eth_wishbone.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/timescale.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
      FILE 
      {
        filepath = "hdl/xilinx_dist_ram_16x32.v";
        use_in_simulation = "1";
        use_in_synthesis = "1";
      }
    }
  }
  SOPC_Builder_Version = "5.00";
  COMPONENT_BUILDER 
  {
    CACHED_HDL_INFO 
    {
      # cached hdl info, emitted by cbGuinevereApp.CBFrameRealtime.getDocumentCachedHDLInfoSection:123
      # used only by Component Builder
      FILE bidirection_io.v
      {
        file_mod = "Wed Mar 01 14:56:41 CST 2006";
        quartus_map_start = "Wed Mar 01 15:20:34 CST 2006";
        quartus_map_finished = "Wed Mar 01 15:20:38 CST 2006";
        #found 1 valid modules
        WRAPPER bidirection_io
        {
          CLASS bidirection_io
          {
            MODULE_DEFAULTS 
            {
              class = "bidirection_io";
              class_version = "1.0";
              SYSTEM_BUILDER_INFO 
              {
                Instantiate_In_System_Module = "1";
              }
              SLAVE avalon_slave_0
              {
                SYSTEM_BUILDER_INFO 
                {
                  Bus_Type = "avalon";
                }
                PORT_WIRING 
                {
                  PORT in_port
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT port_oe
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT out_port
                  {
                    width = "1";
                    width_expression = "";
                    direction = "output";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT bir_port
                  {
                    width = "1";
                    width_expression = "";
                    direction = "inout";
                    type = "export";
                    is_shared = "0";
                  }
                }
              }
            }
            USER_INTERFACE 
            {
              USER_LABELS 
              {
                name = "bidirection_io";
                technology = "imported components";
              }
            }
            CB_GENERATOR 
            {
              top_module_name = "bidirection_io";
              emit_system_h = "0";
              HDL_FILES 
              {
                FILE 
                {
                  filepath = "E:/IP/eth_wb_an/bidirection_io.v";
                  use_in_simulation = "1";
                  use_in_synthesis = "1";
                }
              }
            }
            SOPC_Builder_Version = "0.0";
          }
        }
      }
      FILE eth_clockgen.v
      {
        file_mod = "Wed Mar 09 02:08:58 CST 2005";
        quartus_map_start = "Wed Mar 01 15:20:39 CST 2006";
        quartus_map_finished = "Wed Mar 01 15:20:42 CST 2006";
        #found 1 valid modules
        WRAPPER eth_clockgen
        {
          CLASS eth_clockgen
          {
            MODULE_DEFAULTS 
            {
              class = "eth_clockgen";
              class_version = "1.0";
              SYSTEM_BUILDER_INFO 
              {
                Instantiate_In_System_Module = "1";
              }
              SLAVE avalon_slave_0
              {
                SYSTEM_BUILDER_INFO 
                {
                  Bus_Type = "avalon";
                }
                PORT_WIRING 
                {
                  PORT Clk
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";
                  }
                  PORT Reset
                  {
                    width = "1";
                    width_expression = "";
                    direction = "input";
                    type = "export";
                    is_shared = "0";