class.ptf

网卡的IP核

#
# This class.ptf file built by Component Editor
# 2006.03.01.15:28:11
#
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CLASS eth_wb_an
{
  MODULE_DEFAULTS 
  {
    class = "eth_wb_an";
    class_version = "1.0";
    SYSTEM_BUILDER_INFO 
    {
      Instantiate_In_System_Module = "1";
      Top_Level_Ports_Are_Enumerated = "1";
    }
    COMPONENT_BUILDER 
    {
      GLS_SETTINGS 
      {
      }
    }
    PORT_WIRING 
    {
      PORT CLK
      {
        width = "1";
        width_expression = "";
        direction = "input";
        type = "clk";
        is_shared = "0";
      }
      PORT RESET
      {
        width = "1";
        width_expression = "";
        direction = "input";
        type = "reset";
        is_shared = "0";
      }
      PORT TX_CLK
      {
        width = "1";
        width_expression = "";
        direction = "input";
        type = "export";
        is_shared = "0";
      }
      PORT RX_CLK
      {
        width = "1";
        width_expression = "";
        direction = "input";
        type = "export";
        is_shared = "0";
      }
      PORT RX_DV
      {
        width = "1";
        width_expression = "";
        direction = "input";
        type = "export";
        is_shared = "0";
      }
      PORT RX_ER
      {
        width = "1";
        width_expression = "";
        direction = "input";
        type = "export";
        is_shared = "0";
      }
      PORT COL
      {
        width = "1";
        width_expression = "";
        direction = "input";
        type = "export";
        is_shared = "0";
      }
      PORT CRS
      {
        width = "1";
        width_expression = "";
        direction = "input";
        type = "export";
        is_shared = "0";
      }
      PORT RXD
      {
        width = "4";
        width_expression = "";
        direction = "input";
        type = "export";
        is_shared = "0";
      }
      PORT TX_EN
      {
        width = "1";
        width_expression = "";
        direction = "output";
        type = "export";
        is_shared = "0";
      }
      PORT TX_ER
      {
        width = "1";
        width_expression = "";
        direction = "output";
        type = "export";
        is_shared = "0";
      }
      PORT MDC
      {
        width = "1";
        width_expression = "";
        direction = "output";
        type = "export";
        is_shared = "0";
      }
      PORT MDDIS
      {
        width = "1";
        width_expression = "";
        direction = "output";
        type = "export";
        is_shared = "0";
      }
      PORT TXD
      {
        width = "4";
        width_expression = "";
        direction = "output";
        type = "export";
        is_shared = "0";
      }
      PORT MDIO
      {
        width = "1";
        width_expression = "";
        direction = "inout";
        type = "export";
        is_shared = "0";
      }
    }
    SIMULATION 
    {
      DISPLAY 
      {
        SIGNAL x101
        {
          name = "eth_wb_an/global_signals";
          format = "Divider";
        }
        SIGNAL x102
        {
          name = "CLK";
        }
        SIGNAL x103
        {
          name = "RESET";
        }
        SIGNAL x104
        {
          name = "TX_CLK";
        }
        SIGNAL x105
        {
          name = "RX_CLK";
        }
        SIGNAL x106
        {
          name = "RX_DV";
        }
        SIGNAL x107
        {
          name = "RX_ER";
        }
        SIGNAL x108
        {
          name = "COL";
        }
        SIGNAL x109
        {
          name = "CRS";
        }
        SIGNAL x110
        {
          name = "RXD";
          radix = "hexadecimal";
        }
        SIGNAL x111
        {
          name = "TX_EN";
        }
        SIGNAL x112
        {
          name = "TX_ER";
        }
        SIGNAL x113
        {
          name = "MDC";
        }
        SIGNAL x114
        {
          name = "MDDIS";
        }
        SIGNAL x115
        {
          name = "TXD";
          radix = "hexadecimal";
        }
        SIGNAL x116
        {
          name = "MDIO";
        }
        SIGNAL x117
        {
          name = "eth_wb_an/avalon_slave_0";
          format = "Divider";
        }
        SIGNAL x118
        {
          name = "write";
        }
        SIGNAL x119
        {
          name = "chipselect";
        }
        SIGNAL x120
        {
          name = "address";
        }
        SIGNAL x121
        {
          name = "byteenable";
          format = "Logic";
        }
        SIGNAL x122
        {
          name = "writedata";
          radix = "hexadecimal";
        }
        SIGNAL x123
        {
          name = "waitrequst_n";
        }
        SIGNAL x124
        {
          name = "irq";
        }
        SIGNAL x125
        {
          name = "readdata";
          radix = "hexadecimal";
        }
        SIGNAL x126
        {
          name = "eth_wb_an/avalon_master_0";
          format = "Divider";
        }
        SIGNAL x127
        {
          name = "m_waitrequst_n";
        }
        SIGNAL x128
        {
          name = "m_readdata";
          radix = "hexadecimal";
        }
        SIGNAL x129
        {
          name = "m_write";
        }
        SIGNAL x130
        {
          name = "m_read";
        }
        SIGNAL x131
        {
          name = "m_address";
          radix = "hexadecimal";
        }
        SIGNAL x132
        {
          name = "m_byteenable";
          radix = "hexadecimal";
        }
        SIGNAL x133
        {
          name = "m_writedata";
          radix = "hexadecimal";
        }
      }
    }
    SLAVE avalon_slave_0
    {
      SYSTEM_BUILDER_INFO 
      {
        Bus_Type = "avalon";
        Address_Width = "-1";
        Address_Alignment = "dynamic";
        Data_Width = "32";
        Has_Base_Address = "1";
        Has_IRQ = "1";
        Setup_Time = "0";
        Hold_Time = "0";
        Read_Wait_States = "peripheral_controlled";
        Write_Wait_States = "peripheral_controlled";
        Read_Latency = "0";
        Maximum_Pending_Read_Transactions = "0";
        Is_Printable_Device = "0";
        Is_Memory_Device = "1";
        Is_Readable = "1";
        Is_Writable = "1";
        Minimum_Uninterrupted_Run_Length = "1";
      }
      COMPONENT_BUILDER 
      {
        AVS_SETTINGS 
        {
          Setup_Value = "0";
          Read_Wait_Value = "1";
          Write_Wait_Value = "1";
          Hold_Value = "0";
          Timing_Units = "cycles";
          Read_Latency_Value = "0";
          Max_Pending_Read_Transactions_Value = "1";
          Address_Alignment = "dynamic";
          Is_Printable_Device = "0";
          interface_name = "Avalon Slave";
          Minimum_Arbitration_Shares = "1";
          external_wait = "1";
          Is_Memory_Device = "1";
        }
      }
      PORT_WIRING 
      {
        PORT write
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "write";
          is_shared = "0";
        }
        PORT chipselect
        {
          width = "1";
          width_expression = "";
          direction = "input";
          type = "chipselect";
          is_shared = "0";
        }
        PORT address
        {
          width = "-1";
          width_expression = "11..2";
          direction = "input";
          type = "address";
          is_shared = "0";
        }
        PORT byteenable
        {
          width = "4";
          width_expression = "";
          direction = "input";
          type = "byteenable";
          is_shared = "0";
        }
        PORT writedata
        {
          width = "32";
          width_expression = "";
          direction = "input";
          type = "writedata";
          is_shared = "0";
        }
        PORT waitrequst_n
        {
          width = "1";
          width_expression = "";
          direction = "output";
          type = "waitrequest_n";
          is_shared = "0";
        }
        PORT irq
        {
          width = "1";
          width_expression = "";
          direction = "output";
          type = "irq";
          is_shared = "0";
        }
        PORT readdata
        {
          width = "32";
          width_expression = "";
          direction = "output";
          type = "readdata";
          is_shared = "0";
        }
      }
    }
    MASTER avalon_master_0
    {
      SYSTEM_BUILDER_INFO 
      {
        Bus_Type = "avalon";
        Address_Width = "32";
        Data_Width = "32";
        Do_Stream_Reads = "0";
        Do_Stream_Writes = "0";
        Is_Asynchronous = "0";
        Has_IRQ = "0";
        Irq_Scheme = "none";
        Interrupt_Range = "";
        Is_Readable = "1";
        Is_Writable = "1";
        Register_Outgoing_Signals = "0";
      }
      COMPONENT_BUILDER 
      {
        AVM_SETTINGS 
        {
          stream_reads = "0";
          stream_writes = "0";
          irq_width = "0";
          irq_number_width = "0";
          irq_scheme = "none";
          Is_Asynchronous = "0";
        }
      }
      PORT_WIRING 
      {
        PORT m_waitrequst_n
        {
          width = "1";
          width_expression = "";