sine_rom.tan.summary

在quartus软件下用VHDL语言实现DDS

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : 7.684 ns
From           : address[11]
To             : altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg11
From Clock     : 
To Clock       : clock
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 9.120 ns
From           : altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[6]
To             : q[6]
From Clock     : clock
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : -4.644 ns
From           : address[1]
To             : altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg1
From Clock     : 
To Clock       : clock
Failed Paths   : 0

Type           : Clock Setup: 'clock'
Slack          : N/A
Required Time  : None
Actual Time    : 197.01 MHz ( period = 5.076 ns )
From           : altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a0~porta_address_reg11
To             : altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|q_a[0]
From Clock     : clock
To Clock       : clock
Failed Paths   : 0

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 0

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