fpq.vhd

来自「在quartus软件下用VHDL语言实现DDS」· VHDL 代码 · 共 27 行

library ieee;
use ieee.std_logic_1164.all;

entity fpq is
  generic ( n:integer:=10);
  port ( clk:in std_logic;
         en: in std_logic;
         clkout:out std_logic);
end fpq;

architecture behavior of fpq is
  signal temp : integer range n downto 0;
 begin
  process (clk,temp,en)
    begin
      if en='1' then
        if (clk'event and clk='1') then
          if temp=n-1 then temp<=0;
                           clkout<='1';
            else
              temp<=temp+1;
              clkout<='0';
           end if;
         end if;
       end if;
   end process;
end behavior;