m8.vhd

在quartus软件下用VHDL语言实现DDS

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.std_logic_unsigned.all;

entity m8 is
port (
  clk:in std_logic;
  a,b,c:out std_logic
        );
end m8;

architecture behavior of m8 is
signal m8t:std_logic_vector(2 downto 0);
begin 
  process(clk)
   begin
      if (clk'event and clk='1')then
        if m8t="111"  then
           m8t<="000";
        else
          m8t<=m8t+1;
        end if;
       end if;
   end process;
a<=m8t(0);
b<=m8t(1);
c<=m8t(2);
end behavior;