dds.tan.rpt

来自「在quartus软件下用VHDL语言实现DDS」· RPT 代码 · 共 251 行 · 第 1/5 页

Timing Analyzer report for dds
Thu Apr 03 15:46:02 2008
Version 5.0 Build 148 04/26/2005 SJ Full Version


---------------------
; Table of Contents ;
---------------------
  1. Legal Notice
  2. Timing Analyzer Summary
  3. Timing Analyzer Settings
  4. Clock Settings Summary
  5. Clock Setup: 'clk'
  6. Clock Hold: 'clk'
  7. tsu
  8. tco
  9. tpd
 10. th
 11. Timing Analyzer Messages



----------------
; Legal Notice ;
----------------
Copyright (C) 1991-2005 Altera Corporation
Your use of Altera Corporation's design tools, logic functions 
and other software and tools, and its AMPP partner logic       
functions, and any output files any of the foregoing           
(including device programming or simulation files), and any    
associated documentation or information are expressly subject  
to the terms and conditions of the Altera Program License      
Subscription Agreement, Altera MegaCore Function License       
Agreement, or other applicable license agreement, including,   
without limitation, that your use is for the sole purpose of   
programming logic devices manufactured by Altera and sold by   
Altera or its authorized distributors.  Please refer to the    
applicable agreement for further details.



+-------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
; Timing Analyzer Summary                                                                                                                                                                                                                                                                                           ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+---------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Type                         ; Slack                                    ; Required Time ; Actual Time                      ; From                          ; To                                                                                                            ; From Clock ; To Clock ; Failed Paths ;
+------------------------------+------------------------------------------+---------------+----------------------------------+-------------------------------+---------------------------------------------------------------------------------------------------------------+------------+----------+--------------+
; Worst-case tsu               ; N/A                                      ; None          ; -1.254 ns                        ; phone                         ; xiaochan:inst1|inst8                                                                                          ;            ; clk      ; 0            ;
; Worst-case tco               ; N/A                                      ; None          ; 40.119 ns                        ; xianshi:inst6|m8:inst1|m8t[1] ; a                                                                                                             ; clk        ;          ; 0            ;
; Worst-case tpd               ; N/A                                      ; None          ; 18.705 ns                        ; addr1                         ; DA1[6]                                                                                                        ;            ;          ; 0            ;
; Worst-case th                ; N/A                                      ; None          ; 2.741 ns                         ; reset                         ; xiaochan:inst1|inst                                                                                           ;            ; clk      ; 0            ;
; Clock Setup: 'clk'           ; N/A                                      ; None          ; 58.41 MHz ( period = 17.121 ns ) ; counter:inst2|temp_pht[8]     ; sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9 ; clk        ; clk      ; 0            ;