dds.tan.summary

在quartus软件下用VHDL语言实现DDS

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Timing Analyzer Summary
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Type           : Worst-case tsu
Slack          : N/A
Required Time  : None
Actual Time    : -1.254 ns
From           : phone
To             : xiaochan:inst1|inst8
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Worst-case tco
Slack          : N/A
Required Time  : None
Actual Time    : 40.119 ns
From           : xianshi:inst6|m8:inst1|m8t[1]
To             : a
From Clock     : clk
To Clock       : 
Failed Paths   : 0

Type           : Worst-case tpd
Slack          : N/A
Required Time  : None
Actual Time    : 18.705 ns
From           : addr1
To             : DA1[6]
From Clock     : 
To Clock       : 
Failed Paths   : 0

Type           : Worst-case th
Slack          : N/A
Required Time  : None
Actual Time    : 2.741 ns
From           : reset
To             : xiaochan:inst1|inst
From Clock     : 
To Clock       : clk
Failed Paths   : 0

Type           : Clock Setup: 'clk'
Slack          : N/A
Required Time  : None
Actual Time    : 58.41 MHz ( period = 17.121 ns )
From           : counter:inst2|temp_pht[8]
To             : sine_rom:inst31|altsyncram:altsyncram_component|altsyncram_0qr:auto_generated|ram_block1a5~porta_address_reg9
From Clock     : clk
To Clock       : clk
Failed Paths   : 0

Type           : Clock Hold: 'clk'
Slack          : Not operational: Clock Skew > Data Delay
Required Time  : None
Actual Time    : N/A
From           : cef:inst3|m10:inst1|temp[0]
To             : cef:inst3|lock:inst5|out0[0]
From Clock     : clk
To Clock       : clk
Failed Paths   : 8

Type           : Total number of failed paths
Slack          : 
Required Time  : 
Actual Time    : 
From           : 
To             : 
From Clock     : 
To Clock       : 
Failed Paths   : 8

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