counter.vhd

在quartus软件下用VHDL语言实现DDS

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity counter is
port( reset:in std_logic;
      lj,ph:in std_logic;
      res_lj:out std_logic_vector(3 downto 0);
      res_ph:out std_logic_vector(11 downto 0);
      dis_ljone,dis_ljten,dis_phone,dis_phten:out std_logic_vector(3 downto 0)
     );
end counter;

architecture behavior of counter is
signal temp_lj:std_logic_vector(3 downto 0);
signal temp_ph:std_logic_vector(3 downto 0);
signal temp_pht:std_logic_vector(11 downto 0);
begin

  process(reset,lj)
    begin
      if ( reset='1' ) then
         temp_lj<="0000";
        elsif (lj'event and lj='1')then
           if(temp_lj="1111")then  
              temp_lj<="0000";
             else temp_lj<=temp_lj+'1';
           end if;
      end if;
   res_lj<=temp_lj;
   if(temp_lj>"1001") then
         dis_ljone<=temp_lj-"1010";
        dis_ljten<="0001";
      else dis_ljone<=temp_lj;
           dis_ljten<="0000";
    end if ;
  end process;

  process(reset,ph)
    begin
      if ( reset='1' ) then
         temp_ph<="0000";
        elsif (ph'event and ph='1')then
           if(temp_ph="1111")then  temp_ph<="0000";
             else temp_ph<=temp_ph+1;
            end if;
           if(temp_pht="111100000000")then temp_pht<="000000000000";
             else temp_pht<=temp_pht+"000100000000";
            end if;
       end if;
   if(temp_ph>"1001") then
         dis_phone<=temp_ph-"1010";
         dis_phten<="0001";
      else dis_phone<=temp_ph;
           dis_phten<="0000";
    end if ;
res_ph<=temp_pht;
  end process;
end behavior;