dds.fit.summary

在quartus软件下用VHDL语言实现DDS

Flow Status : Successful - Thu Apr 03 15:45:56 2008
Quartus II Version : 5.0 Build 148 04/26/2005 SJ Full Version
Revision Name : dds
Top-level Entity Name : dds
Family : Cyclone
Device : EP1C12Q240C8
Timing Models : Final
Met timing requirements : N/A
Total logic elements : 191 / 12,060 ( 1 % )
Total pins : 45 / 173 ( 26 % )
Total virtual pins : 0
Total memory bits : 204,800 / 239,616 ( 85 % )
Total PLLs : 0 / 2 ( 0 % )