dds.map.rpt

在quartus软件下用VHDL语言实现DDS

; MAXIMUM_DEPTH                      ; 0                             ; Untyped                 ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                        ; Untyped                 ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                        ; Untyped                 ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                        ; Untyped                 ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                        ; Untyped                 ;
; DEVICE_FAMILY                      ; Cyclone                       ; Untyped                 ;
; CBXI_PARAMETER                     ; altsyncram_0qr                ; Untyped                 ;
+------------------------------------+-------------------------------+-------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+---------------------------------------------------------------------------------------------+
; Parameter Settings for User Entity Instance: cos_rom:inst38|altsyncram:altsyncram_component ;
+------------------------------------+----------------------------+---------------------------+
; Parameter Name                     ; Value                      ; Type                      ;
+------------------------------------+----------------------------+---------------------------+
; BYTE_SIZE_BLOCK                    ; 8                          ; Untyped                   ;
; AUTO_CARRY_CHAINS                  ; ON                         ; AUTO_CARRY                ;
; IGNORE_CARRY_BUFFERS               ; OFF                        ; IGNORE_CARRY              ;
; AUTO_CASCADE_CHAINS                ; ON                         ; AUTO_CASCADE              ;
; IGNORE_CASCADE_BUFFERS             ; OFF                        ; IGNORE_CASCADE            ;
; OPERATION_MODE                     ; ROM                        ; Untyped                   ;
; WIDTH_A                            ; 10                         ; Integer                   ;
; WIDTHAD_A                          ; 12                         ; Integer                   ;
; NUMWORDS_A                         ; 4096                       ; Integer                   ;
; OUTDATA_REG_A                      ; CLOCK0                     ; Untyped                   ;
; ADDRESS_ACLR_A                     ; NONE                       ; Untyped                   ;
; OUTDATA_ACLR_A                     ; NONE                       ; Untyped                   ;
; WRCONTROL_ACLR_A                   ; NONE                       ; Untyped                   ;
; INDATA_ACLR_A                      ; NONE                       ; Untyped                   ;
; BYTEENA_ACLR_A                     ; NONE                       ; Untyped                   ;
; WIDTH_B                            ; 1                          ; Untyped                   ;
; WIDTHAD_B                          ; 1                          ; Untyped                   ;
; NUMWORDS_B                         ; 1                          ; Untyped                   ;
; INDATA_REG_B                       ; CLOCK1                     ; Untyped                   ;
; WRCONTROL_WRADDRESS_REG_B          ; CLOCK1                     ; Untyped                   ;
; RDCONTROL_REG_B                    ; CLOCK1                     ; Untyped                   ;
; ADDRESS_REG_B                      ; CLOCK1                     ; Untyped                   ;
; OUTDATA_REG_B                      ; UNREGISTERED               ; Untyped                   ;
; BYTEENA_REG_B                      ; CLOCK1                     ; Untyped                   ;
; INDATA_ACLR_B                      ; NONE                       ; Untyped                   ;
; WRCONTROL_ACLR_B                   ; NONE                       ; Untyped                   ;
; ADDRESS_ACLR_B                     ; NONE                       ; Untyped                   ;
; OUTDATA_ACLR_B                     ; NONE                       ; Untyped                   ;
; RDCONTROL_ACLR_B                   ; NONE                       ; Untyped                   ;
; BYTEENA_ACLR_B                     ; NONE                       ; Untyped                   ;
; WIDTH_BYTEENA_A                    ; 1                          ; Integer                   ;
; WIDTH_BYTEENA_B                    ; 1                          ; Untyped                   ;
; RAM_BLOCK_TYPE                     ; AUTO                       ; Untyped                   ;
; BYTE_SIZE                          ; 8                          ; Untyped                   ;
; READ_DURING_WRITE_MODE_MIXED_PORTS ; DONT_CARE                  ; Untyped                   ;
; INIT_FILE                          ; ./cos_rom/cos_biao/cos.mif ; Untyped                   ;
; INIT_FILE_LAYOUT                   ; PORT_A                     ; Untyped                   ;
; MAXIMUM_DEPTH                      ; 0                          ; Untyped                   ;
; CLOCK_ENABLE_INPUT_A               ; NORMAL                     ; Untyped                   ;
; CLOCK_ENABLE_INPUT_B               ; NORMAL                     ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_A              ; NORMAL                     ; Untyped                   ;
; CLOCK_ENABLE_OUTPUT_B              ; NORMAL                     ; Untyped                   ;
; DEVICE_FAMILY                      ; Cyclone                    ; Untyped                   ;
; CBXI_PARAMETER                     ; altsyncram_2gr             ; Untyped                   ;
+------------------------------------+----------------------------+---------------------------+
Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".


+--------------------------------+
; Analysis & Synthesis Equations ;
+--------------------------------+
The equations can be found in D:/dds_bate4/dds.map.eqn.


+-------------------------------+
; Analysis & Synthesis Messages ;
+-------------------------------+
Info: *******************************************************************
Info: Running Quartus II Analysis & Synthesis
    Info: Version 5.0 Build 148 04/26/2005 SJ Full Version
    Info: Processing started: Thu Apr 03 15:45:40 2008
Info: Command: quartus_map --read_settings_files=on --write_settings_files=off dds -c dds
Info: Found 2 design units, including 1 entities, in source file cos_rom/cos_rom.vhd
    Info: Found design unit 1: cos_rom-SYN
    Info: Found entity 1: cos_rom
Info: Found 2 design units, including 1 entities, in source file juxing_rom/juxing_rom.vhd
    Info: Found design unit 1: juxing_rom-SYN
    Info: Found entity 1: juxing_rom
Info: Found 2 design units, including 1 entities, in source file juchi_rom/juchi_rom.vhd
    Info: Found design unit 1: juchi_rom-SYN
    Info: Found entity 1: juchi_rom
Info: Found 2 design units, including 1 entities, in source file sanjiao_rom/sanjiao_rom.vhd
    Info: Found design unit 1: sanjiao_rom-SYN
    Info: Found entity 1: sanjiao_rom
Info: Found 2 design units, including 1 entities, in source file sine_rom/sine_rom.vhd
    Info: Found design unit 1: sine_rom-SYN
    Info: Found entity 1: sine_rom
Info: Found 2 design units, including 1 entities, in source file fpq.vhd
    Info: Found design unit 1: fpq-behavior
    Info: Found entity 1: fpq
Info: Found 1 design units, including 1 entities, in source file fp.bdf
    Info: Found entity 1: fp
Info: Found 1 design units, including 1 entities, in source file dds.bdf
    Info: Found entity 1: dds
Info: Found 1 design units, including 1 entities, in source file xiaochan.bdf
    Info: Found entity 1: xiaochan
Info: Found 2 design units, including 1 entities, in source file counter.vhd
    Info: Found design unit 1: counter-behavior
    Info: Found entity 1: counter
Warning: Can't analyze file -- file D:/dds_bate4/jeilia.vhd is missing
Info: Found 2 design units, including 1 entities, in source file phase_add.vhd
    Info: Found design unit 1: phase_add-behavior
    Info: Found entity 1: phase_add
Warning: Can't analyze file -- file D:/dds_bate4/choose.vhd is missing
Info: Found 1 design units, including 1 entities, in source file cef.bdf
    Info: Found entity 1: cef
Info: Found 2 design units, including 1 entities, in source file m10.vhd
    Info: Found design unit 1: m10-behavior
    Info: Found entity 1: m10
Info: Found 2 design units, including 1 entities, in source file lock.vhd
    Info: Found design unit 1: lock-behavior
    Info: Found entity 1: lock
Info: Found 2 design units, including 1 entities, in source file mux8_1.vhd
    Info: Found design unit 1: mux8_1-behavior
    Info: Found entity 1: mux8_1
Info: Found 1 design units, including 1 entities, in source file xianshi.bdf
    Info: Found entity 1: xianshi
Info: Found 2 design units, including 1 entities, in source file m8.vhd
    Info: Found design unit 1: m8-behavior
    Info: Found entity 1: m8
Info: Found 2 design units, including 1 entities, in source f