phase_add.vhd

来自「在quartus软件下用VHDL语言实现DDS」· VHDL 代码 · 共 18 行

library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;

entity phase_add is
port(origin:in std_logic_vector(11 downto 0);
     phase :in std_logic_vector(11 downto 0);
     result:out std_logic_vector(11 downto 0)
     );
end phase_add;

architecture behavior of phase_add is
begin
  process (phase,origin)
    begin
      result<=origin+phase;
    end process;
end behavior;