frequency.map.eqn

次源码实现一个扩频接收机系统

S261L61 = W1_q_a[6] $ (!S261L61_carry_eqn);

--S261L71 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~99COUT
--operation mode is arithmetic

S261L71 = CARRY(W1_q_a[6] # !S261L51);


--X1L7 is lpm_mux:inst90|mux_1td:auto_generated|w_result170w~137
--operation mode is normal

X1L7 = J6_dffs[1] & J6_dffs[0] & W1_q_a[6] # !J6_dffs[0] & S261L61 # !J6_dffs[1] & W1_q_a[6] $ (J6_dffs[0]);


--W1_q_a[5] is lpm_rom:inst87|altrom:srom|altsyncram:rom_block|altsyncram_rfm:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
W1_q_a[5]_PORT_A_address = BUS(S57L63, D1L6, D1L8, D1L01, D1L21, D1L41, D1L61, D1L81, D1L02, D1L22);
W1_q_a[5]_PORT_A_address_reg = DFFE(W1_q_a[5]_PORT_A_address, W1_q_a[5]_clock_0, , , );
W1_q_a[5]_clock_0 = M1_safe_q[7];
W1_q_a[5]_clock_1 = M1_safe_q[7];
W1_q_a[5]_PORT_A_data_out = MEMORY(, , W1_q_a[5]_PORT_A_address_reg, , , , , , W1_q_a[5]_clock_0, W1_q_a[5]_clock_1, , , , );
W1_q_a[5]_PORT_A_data_out_reg = DFFE(W1_q_a[5]_PORT_A_data_out, W1_q_a[5]_clock_1, , , );
W1_q_a[5] = W1_q_a[5]_PORT_A_data_out_reg[0];


--S261L41 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~98
--operation mode is arithmetic

S261L41_carry_eqn = S261L31;
S261L41 = W1_q_a[5] $ (S261L41_carry_eqn);

--S261L51 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~98COUT
--operation mode is arithmetic

S261L51 = CARRY(!W1_q_a[5] & !S261L31);


--X1L6 is lpm_mux:inst90|mux_1td:auto_generated|w_result145w~137
--operation mode is normal

X1L6 = J6_dffs[1] & J6_dffs[0] & W1_q_a[5] # !J6_dffs[0] & S261L41 # !J6_dffs[1] & W1_q_a[5] $ (J6_dffs[0]);


--W1_q_a[4] is lpm_rom:inst87|altrom:srom|altsyncram:rom_block|altsyncram_rfm:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
W1_q_a[4]_PORT_A_address = BUS(S57L63, D1L6, D1L8, D1L01, D1L21, D1L41, D1L61, D1L81, D1L02, D1L22);
W1_q_a[4]_PORT_A_address_reg = DFFE(W1_q_a[4]_PORT_A_address, W1_q_a[4]_clock_0, , , );
W1_q_a[4]_clock_0 = M1_safe_q[7];
W1_q_a[4]_clock_1 = M1_safe_q[7];
W1_q_a[4]_PORT_A_data_out = MEMORY(, , W1_q_a[4]_PORT_A_address_reg, , , , , , W1_q_a[4]_clock_0, W1_q_a[4]_clock_1, , , , );
W1_q_a[4]_PORT_A_data_out_reg = DFFE(W1_q_a[4]_PORT_A_data_out, W1_q_a[4]_clock_1, , , );
W1_q_a[4] = W1_q_a[4]_PORT_A_data_out_reg[0];


--S261L21 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~97
--operation mode is arithmetic

S261L21_carry_eqn = S261L11;
S261L21 = W1_q_a[4] $ (!S261L21_carry_eqn);

--S261L31 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~97COUT
--operation mode is arithmetic

S261L31 = CARRY(W1_q_a[4] # !S261L11);


--X1L5 is lpm_mux:inst90|mux_1td:auto_generated|w_result120w~137
--operation mode is normal

X1L5 = J6_dffs[1] & J6_dffs[0] & W1_q_a[4] # !J6_dffs[0] & S261L21 # !J6_dffs[1] & W1_q_a[4] $ (J6_dffs[0]);


--W1_q_a[3] is lpm_rom:inst87|altrom:srom|altsyncram:rom_block|altsyncram_rfm:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
W1_q_a[3]_PORT_A_address = BUS(S57L63, D1L6, D1L8, D1L01, D1L21, D1L41, D1L61, D1L81, D1L02, D1L22);
W1_q_a[3]_PORT_A_address_reg = DFFE(W1_q_a[3]_PORT_A_address, W1_q_a[3]_clock_0, , , );
W1_q_a[3]_clock_0 = M1_safe_q[7];
W1_q_a[3]_clock_1 = M1_safe_q[7];
W1_q_a[3]_PORT_A_data_out = MEMORY(, , W1_q_a[3]_PORT_A_address_reg, , , , , , W1_q_a[3]_clock_0, W1_q_a[3]_clock_1, , , , );
W1_q_a[3]_PORT_A_data_out_reg = DFFE(W1_q_a[3]_PORT_A_data_out, W1_q_a[3]_clock_1, , , );
W1_q_a[3] = W1_q_a[3]_PORT_A_data_out_reg[0];


--S261L01 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~96
--operation mode is arithmetic

S261L01_carry_eqn = S261L9;
S261L01 = W1_q_a[3] $ (S261L01_carry_eqn);

--S261L11 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~96COUT
--operation mode is arithmetic

S261L11 = CARRY(!W1_q_a[3] & !S261L9);


--X1L4 is lpm_mux:inst90|mux_1td:auto_generated|w_result95w~137
--operation mode is normal

X1L4 = J6_dffs[1] & J6_dffs[0] & W1_q_a[3] # !J6_dffs[0] & S261L01 # !J6_dffs[1] & W1_q_a[3] $ (J6_dffs[0]);


--W1_q_a[2] is lpm_rom:inst87|altrom:srom|altsyncram:rom_block|altsyncram_rfm:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
W1_q_a[2]_PORT_A_address = BUS(S57L63, D1L6, D1L8, D1L01, D1L21, D1L41, D1L61, D1L81, D1L02, D1L22);
W1_q_a[2]_PORT_A_address_reg = DFFE(W1_q_a[2]_PORT_A_address, W1_q_a[2]_clock_0, , , );
W1_q_a[2]_clock_0 = M1_safe_q[7];
W1_q_a[2]_clock_1 = M1_safe_q[7];
W1_q_a[2]_PORT_A_data_out = MEMORY(, , W1_q_a[2]_PORT_A_address_reg, , , , , , W1_q_a[2]_clock_0, W1_q_a[2]_clock_1, , , , );
W1_q_a[2]_PORT_A_data_out_reg = DFFE(W1_q_a[2]_PORT_A_data_out, W1_q_a[2]_clock_1, , , );
W1_q_a[2] = W1_q_a[2]_PORT_A_data_out_reg[0];


--S261L8 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~95
--operation mode is arithmetic

S261L8_carry_eqn = S261L7;
S261L8 = W1_q_a[2] $ (!S261L8_carry_eqn);

--S261L9 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~95COUT
--operation mode is arithmetic

S261L9 = CARRY(W1_q_a[2] # !S261L7);


--X1L3 is lpm_mux:inst90|mux_1td:auto_generated|w_result70w~137
--operation mode is normal

X1L3 = J6_dffs[1] & J6_dffs[0] & W1_q_a[2] # !J6_dffs[0] & S261L8 # !J6_dffs[1] & W1_q_a[2] $ (J6_dffs[0]);


--W1_q_a[1] is lpm_rom:inst87|altrom:srom|altsyncram:rom_block|altsyncram_rfm:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
W1_q_a[1]_PORT_A_address = BUS(S57L63, D1L6, D1L8, D1L01, D1L21, D1L41, D1L61, D1L81, D1L02, D1L22);
W1_q_a[1]_PORT_A_address_reg = DFFE(W1_q_a[1]_PORT_A_address, W1_q_a[1]_clock_0, , , );
W1_q_a[1]_clock_0 = M1_safe_q[7];
W1_q_a[1]_clock_1 = M1_safe_q[7];
W1_q_a[1]_PORT_A_data_out = MEMORY(, , W1_q_a[1]_PORT_A_address_reg, , , , , , W1_q_a[1]_clock_0, W1_q_a[1]_clock_1, , , , );
W1_q_a[1]_PORT_A_data_out_reg = DFFE(W1_q_a[1]_PORT_A_data_out, W1_q_a[1]_clock_1, , , );
W1_q_a[1] = W1_q_a[1]_PORT_A_data_out_reg[0];


--S261L6 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~94
--operation mode is arithmetic

S261L6 = W1_q_a[1] $ !S261L12;

--S261L7 is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~94COUT
--operation mode is arithmetic

S261L7 = CARRY(!W1_q_a[1] & S261L12);


--X1L2 is lpm_mux:inst90|mux_1td:auto_generated|w_result45w~137
--operation mode is normal

X1L2 = J6_dffs[1] & J6_dffs[0] & W1_q_a[1] # !J6_dffs[0] & S261L6 # !J6_dffs[1] & W1_q_a[1] $ (J6_dffs[0]);


--W1_q_a[0] is lpm_rom:inst87|altrom:srom|altsyncram:rom_block|altsyncram_rfm:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
W1_q_a[0]_PORT_A_address = BUS(S57L63, D1L6, D1L8, D1L01, D1L21, D1L41, D1L61, D1L81, D1L02, D1L22);
W1_q_a[0]_PORT_A_address_reg = DFFE(W1_q_a[0]_PORT_A_address, W1_q_a[0]_clock_0, , , );
W1_q_a[0]_clock_0 = M1_safe_q[7];
W1_q_a[0]_clock_1 = M1_safe_q[7];
W1_q_a[0]_PORT_A_data_out = MEMORY(, , W1_q_a[0]_PORT_A_address_reg, , , , , , W1_q_a[0]_clock_0, W1_q_a[0]_clock_1, , , , );
W1_q_a[0]_PORT_A_data_out_reg = DFFE(W1_q_a[0]_PORT_A_data_out, W1_q_a[0]_clock_1, , , );
W1_q_a[0] = W1_q_a[0]_PORT_A_data_out_reg[0];


--S261_cs_buffer[0] is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cs_buffer[0]
--operation mode is arithmetic

S261_cs_buffer[0] = W1_q_a[0];

--S261_cout[0] is lpm_add_sub:inst57|addcore:adder|a_csnbuffer:result_node|cout[0]
--operation mode is arithmetic

S261_cout[0] = CARRY(!W1_q_a[0]);


--X1L1 is lpm_mux:inst90|mux_1td:auto_generated|w_result15w~137
--operation mode is normal

X1L1 = J6_dffs[1] & J6_dffs[0] & W1_q_a[0] # !J6_dffs[0] & S261_cs_buffer[0] # !J6_dffs[1] & W1_q_a[0] $ (J6_dffs[0]);


--M1_safe_q[6] is INTIGRATOR_FE:inst|lpm_counter:CYCLE_rtl_0|cntr_ia7:auto_generated|safe_q[6]
--operation mode is arithmetic

M1_safe_q[6]_carry_eqn = M1L21;
M1_safe_q[6]_lut_out = M1_safe_q[6] $ (!M1_safe_q[6]_carry_eqn);
M1_safe_q[6] = DFFEAS(M1_safe_q[6]_lut_out, CLK, RESET, , , , , , );

--M1L41 is INTIGRATOR_FE:inst|lpm_counter:CYCLE_rtl_0|cntr_ia7:auto_generated|counter_cella6~COUT
--operation mode is arithmetic

M1L41 = CARRY(M1_safe_q[6] & !M1L21);


--V2_q_a[7] is lpm_rom:inst95|altrom:srom|altsyncram:rom_block|altsyncram_80n:auto_generated|q_a[7]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
V2_q_a[7]_PORT_A_address = BUS(~GND, ~GND, S171L1, S171L3, S171L5, S171L7, S171L9, S171L11, S171L31, S171L51);
V2_q_a[7]_PORT_A_address_reg = DFFE(V2_q_a[7]_PORT_A_address, V2_q_a[7]_clock_0, , , );
V2_q_a[7]_clock_0 = !CLK;
V2_q_a[7]_clock_1 = CLK;
V2_q_a[7]_PORT_A_data_out = MEMORY(, , V2_q_a[7]_PORT_A_address_reg, , , , , , V2_q_a[7]_clock_0, V2_q_a[7]_clock_1, , , , );
V2_q_a[7]_PORT_A_data_out_reg = DFFE(V2_q_a[7]_PORT_A_data_out, V2_q_a[7]_clock_1, , , );
V2_q_a[7] = V2_q_a[7]_PORT_A_data_out_reg[0];


--V2_q_a[6] is lpm_rom:inst95|altrom:srom|altsyncram:rom_block|altsyncram_80n:auto_generated|q_a[6]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
V2_q_a[6]_PORT_A_address = BUS(~GND, ~GND, S171L1, S171L3, S171L5, S171L7, S171L9, S171L11, S171L31, S171L51);
V2_q_a[6]_PORT_A_address_reg = DFFE(V2_q_a[6]_PORT_A_address, V2_q_a[6]_clock_0, , , );
V2_q_a[6]_clock_0 = !CLK;
V2_q_a[6]_clock_1 = CLK;
V2_q_a[6]_PORT_A_data_out = MEMORY(, , V2_q_a[6]_PORT_A_address_reg, , , , , , V2_q_a[6]_clock_0, V2_q_a[6]_clock_1, , , , );
V2_q_a[6]_PORT_A_data_out_reg = DFFE(V2_q_a[6]_PORT_A_data_out, V2_q_a[6]_clock_1, , , );
V2_q_a[6] = V2_q_a[6]_PORT_A_data_out_reg[0];


--V2_q_a[5] is lpm_rom:inst95|altrom:srom|altsyncram:rom_block|altsyncram_80n:auto_generated|q_a[5]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
V2_q_a[5]_PORT_A_address = BUS(~GND, ~GND, S171L1, S171L3, S171L5, S171L7, S171L9, S171L11, S171L31, S171L51);
V2_q_a[5]_PORT_A_address_reg = DFFE(V2_q_a[5]_PORT_A_address, V2_q_a[5]_clock_0, , , );
V2_q_a[5]_clock_0 = !CLK;
V2_q_a[5]_clock_1 = CLK;
V2_q_a[5]_PORT_A_data_out = MEMORY(, , V2_q_a[5]_PORT_A_address_reg, , , , , , V2_q_a[5]_clock_0, V2_q_a[5]_clock_1, , , , );
V2_q_a[5]_PORT_A_data_out_reg = DFFE(V2_q_a[5]_PORT_A_data_out, V2_q_a[5]_clock_1, , , );
V2_q_a[5] = V2_q_a[5]_PORT_A_data_out_reg[0];


--V2_q_a[4] is lpm_rom:inst95|altrom:srom|altsyncram:rom_block|altsyncram_80n:auto_generated|q_a[4]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
V2_q_a[4]_PORT_A_address = BUS(~GND, ~GND, S171L1, S171L3, S171L5, S171L7, S171L9, S171L11, S171L31, S171L51);
V2_q_a[4]_PORT_A_address_reg = DFFE(V2_q_a[4]_PORT_A_address, V2_q_a[4]_clock_0, , , );
V2_q_a[4]_clock_0 = !CLK;
V2_q_a[4]_clock_1 = CLK;
V2_q_a[4]_PORT_A_data_out = MEMORY(, , V2_q_a[4]_PORT_A_address_reg, , , , , , V2_q_a[4]_clock_0, V2_q_a[4]_clock_1, , , , );
V2_q_a[4]_PORT_A_data_out_reg = DFFE(V2_q_a[4]_PORT_A_data_out, V2_q_a[4]_clock_1, , , );
V2_q_a[4] = V2_q_a[4]_PORT_A_data_out_reg[0];


--V2_q_a[3] is lpm_rom:inst95|altrom:srom|altsyncram:rom_block|altsyncram_80n:auto_generated|q_a[3]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
V2_q_a[3]_PORT_A_address = BUS(~GND, ~GND, S171L1, S171L3, S171L5, S171L7, S171L9, S171L11, S171L31, S171L51);
V2_q_a[3]_PORT_A_address_reg = DFFE(V2_q_a[3]_PORT_A_address, V2_q_a[3]_clock_0, , , );
V2_q_a[3]_clock_0 = !CLK;
V2_q_a[3]_clock_1 = CLK;
V2_q_a[3]_PORT_A_data_out = MEMORY(, , V2_q_a[3]_PORT_A_address_reg, , , , , , V2_q_a[3]_clock_0, V2_q_a[3]_clock_1, , , , );
V2_q_a[3]_PORT_A_data_out_reg = DFFE(V2_q_a[3]_PORT_A_data_out, V2_q_a[3]_clock_1, , , );
V2_q_a[3] = V2_q_a[3]_PORT_A_data_out_reg[0];


--V2_q_a[2] is lpm_rom:inst95|altrom:srom|altsyncram:rom_block|altsyncram_80n:auto_generated|q_a[2]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
V2_q_a[2]_PORT_A_address = BUS(~GND, ~GND, S171L1, S171L3, S171L5, S171L7, S171L9, S171L11, S171L31, S171L51);
V2_q_a[2]_PORT_A_address_reg = DFFE(V2_q_a[2]_PORT_A_address, V2_q_a[2]_clock_0, , , );
V2_q_a[2]_clock_0 = !CLK;
V2_q_a[2]_clock_1 = CLK;
V2_q_a[2]_PORT_A_data_out = MEMORY(, , V2_q_a[2]_PORT_A_address_reg, , , , , , V2_q_a[2]_clock_0, V2_q_a[2]_clock_1, , , , );
V2_q_a[2]_PORT_A_data_out_reg = DFFE(V2_q_a[2]_PORT_A_data_out, V2_q_a[2]_clock_1, , , );
V2_q_a[2] = V2_q_a[2]_PORT_A_data_out_reg[0];


--V2_q_a[1] is lpm_rom:inst95|altrom:srom|altsyncram:rom_block|altsyncram_80n:auto_generated|q_a[1]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
V2_q_a[1]_PORT_A_address = BUS(~GND, ~GND, S171L1, S171L3, S171L5, S171L7, S171L9, S171L11, S171L31, S171L51);
V2_q_a[1]_PORT_A_address_reg = DFFE(V2_q_a[1]_PORT_A_address, V2_q_a[1]_clock_0, , , );
V2_q_a[1]_clock_0 = !CLK;
V2_q_a[1]_clock_1 = CLK;
V2_q_a[1]_PORT_A_data_out = MEMORY(, , V2_q_a[1]_PORT_A_address_reg, , , , , , V2_q_a[1]_clock_0, V2_q_a[1]_clock_1, , , , );
V2_q_a[1]_PORT_A_data_out_reg = DFFE(V2_q_a[1]_PORT_A_data_out, V2_q_a[1]_clock_1, , , );
V2_q_a[1] = V2_q_a[1]_PORT_A_data_out_reg[0];


--V2_q_a[0] is lpm_rom:inst95|altrom:srom|altsyncram:rom_block|altsyncram_80n:auto_generated|q_a[0]
--RAM Block Operation Mode: ROM
--Port A Depth: 1024, Port A Width: 1
--Port A Logical Depth: 1024, Port A Logical Width: 8
--Port A Input: Registered, Port A Output: Registered
V2_q_a[0]_PORT_A_address = BUS(~GND, ~GND, S171L1, S171L3, S171L5, S171L7, S171L9, S171L11, S171L31, S171L51);
V2_q_a[0]_PORT_A_address_reg = DFFE(V2_q_a[0]_PORT_A_address, V2_q_a[0]_clock_0, , , );
V2_q_a[0]_clock_0 = !CLK;
V2_q_a[0]_clock_1 = CLK;
V2_q_a[0]_PORT_A_data_out = MEMORY(, , V2_q_a[0]_PORT_A_address_reg, , , , , , V2_q_a[0]_clock_0, V2_q_a[0]_clock_1, , , , );
V2_q_a[0]_PORT_A_data_out_reg = DFFE(V2_q_a[0]_PORT_A_data_out, V2_q_a[0]_clock_1, , , );
V2_q_a[0] = V2_q_a[0]_PORT_A_data_out_reg[0];


--S171L71 is lpm_add_sub:inst94|addcore:adder|a_csnbuffer:result_node|cs_buffer[2]~118
--operation mode is normal

S171L71_carry_eqn = S171L61;
S171L71 = !S171L71_carry_eqn;


--S051L53 is lpm_divide:inst6|sign_div_unsign:divider|alt_u_div:divider|lpm_add_sub:$00049|addcore:adder|a_csnbuffer:result_node|cs_buffer[1]~217
--operation mode is normal

S051L53_carry_eqn = S051L33;
S051L53 = S051L53_carry_eqn;


--E1_lcarry[1] is lpm_abs:inst15|lcarry[1]
--operation mode is arithmetic

E1_lcarry[1]_carry_eqn = E1L3;
E1_lcarry[1] = IDIN[15] $ IDIN[1] $ E1_lcarry[1]_carry_eqn;

--E1L5 is lpm_abs:inst15|lcarry[1]~COUT
--operation mode is arithmetic

E1L5 = CARRY(IDIN[15] $ !IDIN[1] # !E1L3);


--E2_lcarry[14] is lpm_abs:inst18|lcarry[14]
--operation mode is arithmetic

E2_lcarry[14]_carry_eqn = E2L92;
E2_lcarry[14] = QDIN[15] $ QDIN[14] $ !E2_lcarry[14]_carry_eqn;

--E2L33 is lpm_abs:inst18|lcarry[14]~COUT
--operation mode is arithmetic

E2L33 = CARRY(!E2L92 & QDIN[15] $ QDIN[14]);


--P2L4 is lpm_divide:inst6|sign_div_unsign:divider|alt_u_div:divider|selnose[1][1]~495
--operation mode is normal

P2L4 = E1_lcarry[1] & !E2L23;


--E1_lcarry[12] is lpm_abs:inst15|lcarry[12]
--operation mode is arithmetic

E1_lcarry[12]_carry_eqn = E1L5