📄 qd.vhd
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--文件名:qd.vhd
--功 能:抢答器
--说 明:设计了两人的抢答器,分别设有按钮P1,P2(P1对应按键S3,P2对应按键S4)
-- 当按钮1被按下时显示灯1亮即D3亮,同样时按钮2时显示灯D10亮;32秒后
-- 无人抢答的话,自动报警;当有人抢答时除了显示灯亮之外,蜂鸣器会响。
-- 拨盘开关#2为复位键。
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;
entity qd is
Port ( clk : in std_logic; --时钟信号
p1 : in std_logic; --按钮1
p2 : in std_logic; --按钮2
reset : in std_logic; --复位键
cs_led2 : out std_logic;
led1 : out std_logic; --显示灯1
led2 : out std_logic; --显示灯2
led3,led4,led5,led6,led7,led8 : out std_logic;
qq : out std_logic); --蜂鸣器
end qd;
architecture Behavioral of qd is
signal clk1,clk3,a: std_logic;
begin
process(clk) --产生1khz的时钟频率
variable cnt : integer range 0 to 50000;
begin
if clk'event and clk='1' then cnt:=cnt+1;
if cnt<25000 then clk3<='1';
elsif cnt<50000 then clk3<='0';
else cnt:=0;clk3<='0';
end if;
end if;
end process;
process(clk3) --50M分频
variable count: integer range 0 to 1000;
begin
if clk3'event and clk3='1'then count:=count+1;
if count=500 then count:=count+1;clk1<='0';
elsif count>=1000 then count:=0;clk1<='1';
end if;
end if;
end process;
process(clk1,p1,p2)
variable count1 : integer range 31 downto 0;
begin
cs_led2<='1';
if reset='0' then led1<='1';led2<='1';led3<='1';led4<='1';led5<='1';led6<='1';led7<='1';led8<='1'; a<='0';
elsif reset='1'then
if rising_edge(clk1) then count1:=count1-1;
if count1<=0 then led1<='1';led2<='1';led3<='1';led4<='1';led5<='1';led6<='1';led7<='1';led8<='1';a<='1';
elsif p1='0' then led1<='0';led2<='1';led3<='1';led4<='1';led5<='1';led6<='1';led7<='1';led8<='1';a<='1';
elsif p2='0'then led1<='1';led2<='0';led3<='1';led4<='1';led5<='1';led6<='1';led7<='1';led8<='1';a<='1';
end if;
end if;
end if;
end process;
process (reset,a)
begin
if reset='0' then
qq<='1';
elsif a='1'then
qq<=clk3;
end if;
end process;
end Behavioral;
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