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15.14.2 驱动值解析</div>
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当多于一个同步驱动在相同的仿真时间被应用到相同的时钟控制块输出（或<span style="color: #0000FF">inout</span>）的时候，SystemVerilog会检查被驱动值的冲突。当检测到冲突驱动的时候会发布一个运行时错误，并且每一个发生冲突的位都被驱动成<span style="color: #FF0000">X</span>（对一个两态端口会被驱动成<span style="color: #FF0000">0</span>）。 </p>
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例如： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00558"><pre class="Element12"><span style="color: #0000FF">clocking</span> pe <span style="color: #800080">@(</span><span style="color: #0000FF">posedge</span> clk<span style="color: #800080">);</span>
<span style="color: #0000FF">output</span> nibble<span style="color: #800080">;</span> <span style="color: #008000">// 四位输出</span>
<span style="color: #0000FF">endclocking</span>
pe<span style="color: #800080">.</span>nibble <span style="color: #800080"><=</span> <span style="color: #FF0000">4</span><span style="color: #800080">'</span><span style="color: #0000FF">b</span><span style="color: #FF0000">0101</span><span style="color: #800080">;</span>
pe<span style="color: #800080">.</span>nibble <span style="color: #800080"><=</span> <span style="color: #FF0000">4</span><span style="color: #800080">'</span><span style="color: #0000FF">b</span><span style="color: #FF0000">0011</span><span style="color: #800080">;</span></pre></div></div>
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无论<span class="Element146">nibble</span>使一个<span style="color: #0000FF">reg</span>还是一个<span style="color: #0000FF">wire</span>，被驱动的值都是<span style="color: #FF0000">4</span><span style="color: #800080">'</span><span style="color: #0000FF">b</span><span style="color: #FF0000">0xx1</span>。 </p>
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当相同的变量是来自多个时钟控制块的输出的时候，最后一个驱动确定变量的值。这就使得一个单一模块能够通过使用一个不同的时钟控制块来建模每一个活跃沿来对多速率器件（例如一个DDR存储器）建模。例如： </p><div class="Element170">
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<div class="Element13"><div class="Element12" id="code00559"><pre class="Element12"><span style="color: #0000FF">reg</span> j<span style="color: #800080">;</span>
<span style="color: #0000FF">clocking</span> pe <span style="color: #800080">@(</span><span style="color: #0000FF">posedge</span><span style="color: #800080"> </span>clk<span style="color: #800080">);</span>
<span style="color: #0000FF">output</span> j<span style="color: #800080">;</span>
<span style="color: #0000FF">endclocking</span>
<span style="color: #0000FF">clocking</span> ne <span style="color: #800080">@(</span><span style="color: #0000FF">negedge</span> clk<span style="color: #800080">);</span>
<span style="color: #0000FF">output</span> j<span style="color: #800080">;</span>
<span style="color: #0000FF">endclocking</span></pre></div></div>
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变量j是使用不同的时钟控制事件（<span style="color: #0000FF">posedge</span>和<span style="color: #0000FF">negedge</span>）的时钟控制块的输出。当被驱动的时候，变量j的取值应该是被这两个时钟控制块赋值的最近的值。 </p>
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驱动一个线网（也就是通过不同的端口）的时钟控制块会引起线网被驱动成它的被解析的信号值。当一个时钟控制块输出对应于一个线网的时候，会产生一个线网的驱动器，它在更新的时候就好像被一个来自时钟控制块内部的寄存器连续无阻塞赋值一样。</p></div>
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