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8.5 循环语句</div>
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<div class="Element13"><div class="Element12" id="code00277"><pre class="Element12">loop_statement ::= <span style="color: #008000">// 引用自附录A.6.8</span>
<strong><span style="color: #FF0000">forever</span></strong> statement_or_null
| <strong><span style="color: #FF0000">repeat</span></strong> <strong><span style="color: #FF0000">(</span></strong>expression<strong><span style="color: #FF0000">)</span></strong> statement_or_null
| <strong><span style="color: #FF0000">while (</span></strong>expression<strong><span style="color: #FF0000">)</span></strong> statement_or_null
| <strong><span style="color: #FF0000">for (</span></strong>for_initialization<strong><span style="color: #FF0000">;</span></strong> expression<strong><span style="color: #FF0000">;</span></strong> for_step<strong><span style="color: #FF0000">)</span></strong>
statement_or_null
| <strong><span style="color: #FF0000">do</span></strong> statement_or_null <strong><span style="color: #FF0000">while</span></strong> <strong><span style="color: #FF0000">(</span></strong>expression<strong><span style="color: #FF0000">);</span></strong>
| <strong><span style="color: #FF0000">foreach</span></strong> <span style="color: #FF0000">(</span>array_identifier<strong><span style="color: #FF0000">[</span></strong>loop_variables<strong><span style="color: #FF0000">])</span></strong> statement
for_initialization ::=
list_of_variable_assignments
| data_type list_of_variable_assignments {<strong><span style="color: #FF0000">,</span></strong>data_type list_of_variable_assignments}
for_step ::= for_step_assignment {<strong><span style="color: #FF0000">,</span></strong>for_step_assignment}
for_step_assignment ::=
operator_assignment
| inc_or_dec_expression
loop_variables ::= [index_variable_identifier]{<span style="color: #FF0000">,</span>[index_variable_identifier]}</pre></div></div>
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<strong>语法 8-5—循环语句语法（摘录自附录A）</strong></p><p class="Element10">
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Verilog提供了<span style="color: #0000FF">for</span>、<span style="color: #0000FF">while</span>、<span style="color: #0000FF">repeat</span>以及<span style="color: #0000FF">forever</span>循环。SystemVerilog增强了Verilog的<span style="color: #0000FF">for</span>循环，并加入了一个<span style="color: #0000FF">do...while</span>循环和一个<span style="color: #0000FF">foreach</span>循环。</p></div>
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<a href="00846.html" target="topic">第八章 过程语句和控制流</a></p></div>
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描述 </div></td></tr><tr>
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<a href="00589.html" target="topic">8.5.1 do...while循环</a> </div></td><td class="Element206" valign="top" width="50%">
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<a href="00590.html" target="topic">8.5.2 循环的增强</a> </div></td><td class="Element206" valign="top" width="50%">
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在Verilog中，用来控制for循环的变量必须在循环之前声明。如果两个或多个并行程序中的循环使用相同的循环控制变量，那么就有可能出现一个循环修改其它循环还在使用的循环控制变量的情况。<br><br>SystemVerilog加入了在for循环中声明for循环控制变量的能力。这种方式会在循环内产生一个本地变量。其它并行循环不可能偶然地影响这个循环控制变量。例如： </div></td></tr><tr>
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<a href="00591.html" target="topic">8.5.3 foreach循环</a> </div></td><td class="Element206" valign="top" width="50%">
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<span style="color: #0000FF">foreach</span>结构指定在数组元素上的迭代。它的自变量是一个指明任意类型数组（固定尺寸的、动态的、及联合数组）的标识符，然后紧跟着一个包围在方括号内的循环变量的列表。每一个循环变量对应于数组的某一维。<span style="color: #0000FF">foreach</span>结构类似于一个使用数组范围替代一个表达式来指定重复次数的<span style="color: #0000FF">repeat</span>循环。<br><br>例子： </div></td></tr></table></div></div>
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