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这是一本关于verilog编程语言的教程,对学习verilog语言有帮助

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A System Verilog task that is declared in an export declaration and can be enabled from an imported task.&nbsp;</div></td></tr><tr>
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<a href="00836.html" target="topic">Imported task</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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A DPI foreign code subprogram that can call exported tasks and can directly or indirectly consume simulation time.&nbsp;</div></td></tr><tr>
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<a href="00838.html" target="topic">Interface</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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An interface encapsulates the communication between blocks of a design, allowing a smooth migration from abstract system-level design through successive refinement down to lower-level register-transfer and structural views of the design. By encapsulating the communication between blocks, the interface construct also facilitates design re-use. The inclusion of interface capabilities is one of the major advantages of SystemVerilog. Interfaces are covered in Section 19.&nbsp;</div></td></tr><tr>
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<a href="00837.html" target="topic">Integral</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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An integral expression, variable or type is used to represent integral, or integer value They may also be called vectored values. .Integrals may be signed or unsigned, sliced into smaller integral values, or concatenated into larger values.&nbsp;</div></td></tr><tr>
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<a href="00839.html" target="topic">LRM</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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LRM是<strong>L</strong>anguage <strong>R</strong>eference <strong>M</strong>anual的缩写。“SystemVerilog LRM”指的是本文档。“Verilog LRM”指的是IEEE手册“1364-2001 IEEE Standard for Verilog Hardware Description Language 2001”。参见<a href="00889.html" target="topic">附录K</a>中有关这个手册的信息。&nbsp;</div></td></tr><tr>
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<a href="00840.html" target="topic">Open array</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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A DPI array formal argument for which the packed or unpacked dimension size (or both) is not specified and for which interface routines describe the size of corresponding actual arguments at runtime.&nbsp;</div></td></tr><tr>
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<a href="00841.html" target="topic">Packed array</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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Packed array refers to an array where the dimensions are declared before an object name. Packed arrays can have any number of dimensions. A one-dimensional packed array is the same as a vector width declaration in Verilog. Packed arrays provide a mechanism for subdividing a vector into subfields, which can be conveniently accessed as array elements. A packed array differs from an unpacked array, in that the whole array is treated as a single vector for arithmetic operations. Packed arrays are discussed in detail in Section 4.&nbsp;</div></td></tr><tr>
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<a href="00891.html" target="topic">进程</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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进程是一个或多个编程语句的线程，这些编程语句可以独立于其它编程语句执行。Verilog中的每一个<span style="color: #0000FF">initial</span>过程、<span style="color: #0000FF">always</span>过程以及连续赋值语句都是一个独立的进程。这些都是静态的进程。也就是说，每次进程启动运行后，都会有一个进程的结束。SystemVerilog加入了特殊的always过程，它们既可以是静态进程也可以是动态进程。当启动动态进程的时候，它们可以无中止地运行。有关进程的内容在<a href="00858.html" target="topic">第九章</a>提供。&nbsp;</div></td></tr><tr>
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<a href="00893.html" target="topic">信号</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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信号是一个非正式的术语，通常指的是一个变量或线网。它所处的上下文可能会在允许的类型上作进一步的限制。&nbsp;</div></td></tr><tr>
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<a href="00845.html" target="topic">单一类型（Singular）</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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一个单一（singular）表达式、变量或类型代表一个单一的值、符号或句柄。一个单一类型可以是除非压缩结构体、非压缩联合体、或非压缩数组数据类型外的任何类型。&nbsp;</div></td></tr><tr>
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<a href="00842.html" target="topic">SystemVerilog</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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SystemVerilog指的是Accellera为在抽象建模和验证方面扩展IEEE 1364-2001 Verilog标准的能力所建立的标准。SystemVerilog标准的许多特性均在本文档中提供。&nbsp;</div></td></tr><tr>
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<a href="00878.html" target="topic">非压缩数组（Unpacked array）</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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非压缩数组是一种类型的数组，它的数组维数在对象名之后声明。非压缩数组与Verilog中的数组相同，并且可以拥有任意数目的维数。非压缩数组与压缩数组的不同之处在于：非压缩数组作为一个整体不能使用在算术运算中。它的每一个元素必须单独处理。非压缩数组在<a href="00874.html" target="topic">第四章</a>中讨论。&nbsp;</div></td></tr><tr>
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<a href="00843.html" target="topic">Verilog</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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Verilog指的是IEEE 1364-2001 Verilog硬件描述语言（HDL），一般称为Verilog-2001。这个语言在IEEE手册“1364-2001 IEEE Standard for Verilog Hardware Description Language 2001”中描述。参见<a href="00889.html" target="topic">附录K</a>中有关这个手册的相关信息。&nbsp;</div></td></tr><tr>
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<a href="00844.html" target="topic">VPI</a>&nbsp;</div></td><td class="Element206" valign="top" width="50%">
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<strong>V</strong>erilog <strong>P</strong>rocedural <strong>I</strong>nterface的缩写，意为“Verilog程序接口”。它是第三代Verilog编程语言接口（PLI），提供了以面向对象的方式访问Verilog行为对象、结构对象、断言和覆盖对象的能力。&nbsp;</div></td></tr></table></div></div>
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