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<a href="#" onmousedown="showPopup(this, 'popup00864');"><img src="seealsolink.png" border="0" alt="" title=""></a> SystemVerilog 3.1a语言参考手册</div>
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附录J 术语表</div>
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描述 </div></td></tr><tr>
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<a href="00890.html" target="topic">集合</a> </div></td><td class="Element206" valign="top" width="50%">
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一个集合表达式、变量或类型代表了一组单一值。集合类型是任意非压缩结构体、非压缩联合体、或非压缩数组数据类型。集合可以作为一个整体拷贝或比较,但典型情况下不能作为一个整体使用在表达式中。 </div></td></tr><tr>
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<a href="00877.html" target="topic">断言</a> </div></td><td class="Element206" valign="top" width="50%">
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断言是一条某个特性必须为“真”的语句。例如,一个<span class="Element146">read_request</span>信号必须总是在两个时钟内跟着一个<span class="Element146">read_grant</span>信号。断言能够自动检查一个指定的特性是否为“真”,并且,如果特性不为“真”,它能够自动产生一条错误信息。SystemVerilog提供了特殊的断言结构。断言结构在<a href="00868.html" target="topic">第17章</a>中讨论。 </div></td></tr><tr>
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<a href="00693.html" target="topic">Bit-stream</a> </div></td><td class="Element206" valign="top" width="50%">
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A bit-stream type or variables is any type that can be represented as a serial stream of bits. To qualify as a bit-stream type, each and every bit of the type must be individually addressable. This means that a bit-stream type can be any type that does not include a handle, chandle, real, shortreal, or event. </div></td></tr><tr>
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<a href="00698.html" target="topic">Canonical representation</a> </div></td><td class="Element206" valign="top" width="50%">
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A data representation format established by convention into which and from which translations can be made with specialized representations. </div></td></tr><tr>
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<a href="00699.html" target="topic">Constant</a> </div></td><td class="Element206" valign="top" width="50%">
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There are two types of constants in SystemVerilog. Parameters and local parameters are elaboration constants. Their values are calculated before elaboration is complete. Elaboration constants can be used to set the range of array types. The other form of constant is a run-time constant. These are variables that can only be set in an initialization expression using the const qualifier. </div></td></tr><tr>
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<a href="00700.html" target="topic">Context imported task</a> </div></td><td class="Element206" valign="top" width="50%">
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A DPI imported task declared with the 'context' property that is capable of calling exported tasks or functions and capable of accessing System Verilog objects via VPI or PLI calls. </div></td></tr><tr>
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<a href="00733.html" target="topic">Disable protocol</a> </div></td><td class="Element206" valign="top" width="50%">
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A set of conventions for setting, checking and handling disable status. </div></td></tr><tr>
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<a href="00734.html" target="topic">DPI</a> </div></td><td class="Element206" valign="top" width="50%">
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Direct Programming Interface. This is an interface between SystemVerilog and foreign programming languages permitting direct function calls from SystemVerilog to foreign code and from foreign code to SystemVerilog. It has been designed to have low inherent overhead and permit direct exchange of data between SystemVerilog and foreign code. </div></td></tr><tr>
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<a href="00735.html" target="topic">Dynamic</a> </div></td><td class="Element206" valign="top" width="50%">
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A dynamic type or variable is one that can be resized or re-allocated at runtime. Dynamic types include those that contain dynamic arrays, associative arrays, queues, or class handles. </div></td></tr><tr>
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<a href="00803.html" target="topic">Elaboration</a> </div></td><td class="Element206" valign="top" width="50%">
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Elaboration is the process of binding together the components that make up a design. These components can include module instances, primitive instances, interfaces, and the top-level of the design hierarchy. </div></td></tr><tr>
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<a href="00892.html" target="topic">枚举类型</a> </div></td><td class="Element206" valign="top" width="50%">
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枚举数据类型提供了一种能力来声明可以由一组命名值表示的变量。我们可以指定这些值等价的数值。枚举类型可以使用枚举名字而不是枚举值方便地引用或显示。<a href="00370.html" target="topic">3.10节</a>讨论了枚举类型。 </div></td></tr><tr>
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<a href="00804.html" target="topic">Exported task</a> </div></td><td class="Element206" valign="top" width="50%">
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