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26.2 defparam语句</div>
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The SystemVerilog committee has determined, based on the solicitation of input from tool implementers and tools users, that the defparam method of specifying the value of a parameter can be a source of design errors, and can be an impediment to tool implementation. The defparam statement does not provide a capability that cannot be done by another method, which avoids these problems. Therefore, the committee has placed the defparam statement on a deprecation list. This means is that a future revision of the Verilog standard might not require support for this feature. This current standard still requires tools to support the defparam statement. However, users are strongly encouraged to migrate their code to use one of the alternate methods of parameter redefinition. </p>
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Prior to the acceptance of the Verilog-2001 Standard, it was common practice to change one or more parameters of instantiated modules using a separate defparam statement. Defparam statements can be a source of tool complexity and design problems. </p>
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A defparam statement can precede the instance to be modified, can follow the instance to be modified, can be at the end of the file that contains the instance to be modified, can be in a separate file from the instance to be modified, can modify parameters hierarchically that in turn must again be passed to other defparam statements to modify, and can modify the same parameter from two different defparam statements (with undefined results). Due to the many ways that a defparam can modify parameters, a Verilog compiler cannot insure the final parameter values for an instance until after all of the design files are compiled. </p>
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Prior to Verilog-2001, the only other method available to change the values of parameters on instantiated modules was to use implicit in-line parameter redefinition. This method uses #(parameter_value) as part of the module instantiation. Implicit in-line parameter redefinition syntax requires that all parameters up to and including the parameter to be changed must be placed in the correct order, and must be assigned values. </p>
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Verilog-2001 introduced explicit in-line parameter redefinition, in the form #(.parameter_name(value)), as part of the module instantiation. This method gives the capability to pass parameters by name in the instantiation, which supplies all of the necessary parameter information to the model in the instantiation itself. </p>
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The practice of using defparam statements is highly discouraged. Engineers are encouraged to take advantage of the Verilog-2001 explicit in-line parameter redefinition capability. </p>
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See Section 21 for more details on parameters.</p></div>
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